Supplier: Pat Ming Core City Component Mall (being supplied)
Description
The F2806x Piccolo? family of microcontrollers (MCUs) provides the CLA for the C28x core as well as for coupling with highly integrated control peripherals in devices with fewer pins. power supply. The code in this family of devices is compatible with older C28x-based code while providing a high level of analog integration.
An internal regulator enables single supply rail operation. The HRPWM module has been improved to provide dual edge control (FM). An analog comparator with a 10-bit internal reference has been added to control the ePWM output through its direct connection, and the ADC converts over a fixed full-scale range of 0V to 3.3V and supports scaling with the VREFHI/VREFLO reference. the ADC interface has been optimized for low overhead and latency.
Features
High-efficiency 32-bit CPU (TMS320C28x)
90Mhz (11.11ns cycle time)
16 × 16 and 32 × 32 multiply-and-accumulate (MAC) operations
16 × 16 Dual MACs
Harvard Bus architecture
Concatenated Operations
Fast Interrupt Response and Handling
Unified Memory Programming Model
Highly Efficient Code (in C/C++ and Assembly Languages)
Floating-Point Unit (FPU)
Native Single-Precision Floating-Point Operations
Programmable Parallel Accelerators (CLA)
32-Bit Floating Point Accelerator
Code execution independent of the host CPU
Viterbi, Complex Arithmetic, Cyclic Redundancy Check (CRC) Unit (VCU)
Extends the C28x instruction set to support complex multiplications, Viterbi operations, and Cyclic Redundancy Check (CRC)
Embedded memory
Up to 256KB of memory.
Up to 256KB of Flash memory
Up to 100KB of random access memory (RAM)
2KB of one-time programmable (OTP) ROM
6-channel Direct Memory Access (DMA)
Low device and system cost
3.3V single-supply power supply
No need for power-supply sequencing
Integrated power-up reset and undervoltage reset
Low-power mode of operation
No analog support pins
Trailing methodology: small trailing methodology
Support for JTAG boundary-sweep
IEEE Std. 1149.1-1990 Standard Test Access Port and Boundary-Scan Architecture
Timing
Timing p>Two internal zero-pin oscillators
On-chip crystal oscillator/external clock input
Watchdog timer module
Loss-of-clock detection circuitry
Peripheral Interrupt Expansion (PIE) module supporting all peripheral interrupts
Three 32-bit CPU timers
Advanced Control Peripheral
Up to 8 Enhanced Pulse Events
Advanced Control Peripheral
Up to 8 Enhanced Pulse Events
Up to 8 Enhanced Pulse Width Modulator (ePWM) Modules
Total*** 16 PWM channels (8 HRPWM supported)
Independent 16-bit timers in each module
3 Input Enhanced Capture (eCAP) Modules
Up to 4 High Resolution Capture (HRCAP) Modules
12-bit Analog-to-Digital Converter (ADC) with Dual Sample-and-Hold (S/H)
Up to 3.46 Million Samples per Second
Up to 16 Channels
On-chip Temperature Sensor
128-bit Security Key and Lock
Protected Secure Memory Block
Protected Secure Memory Block
Protection against firmware reverse engineering
Serial Port Peripherals
Two Serial Communications Interface (SCI) [UART] Modules
Two Serial Peripheral Interface (SPI) Modules
One Integrated Circuit-to-Circuit (I2C) Bus
One Multi-Channel Buffered Serial Port ( McBSP) bus
An Enhanced Controller Area Network (eCAN)
Universal Serial Bus (USB) 2.0
(See Device Comparison Chart for availability)
Full-speed device mode
Full-speed or Low-speed Host Mode
Up to 54 individually programmable, multiplexed general-purpose input/output (GPIO) pins with input filtering support
Advanced Emulation Features
Analyze and Breakpoint Capabilities
Real-time Debugging via Hardware
Package Options
80-Pin PFP & 100-Pin PZP PowerPAD PowerPAD Thermally Enhanced Thin Quad Flat Pack (HTQFP)
80-pin PN and 100-pin PZ Thin Quad Flat Pack (LQFP)
Temperature Options
T: -40°C to 105°C
S: -40°C to 125°C
Q: -40°C to 125°C (AEC Q100 qualified for automotive applications) Q: -40°C to 125°C (AEC Q100 certified for automotive applications)