Motherboard test card instructions ( code as follows )
00 . The configuration of the system has been displayed; about to control INI19 boot loaded.
01 Processor test 1, processor status verified, if test fails, loop is infinite. Processor register tests are about to begin; unmaskable interrupts are about to be deactivated. CPU register tests are in progress or failing.
02 Determine the type of diagnostic (normal or manufacturing). Keypad buffer *** fails if it has data. Disable non-maskable interrupts; start via ***. CMOS write/read is in progress or failed.
03 Clear 8042 Keyboard Controller with TESTKBRD command (AAH) Power-on *** Completed. ROM BIOS check component is in progress or malfunctioning.
04 Reset the 8042 Keyboard Controller and verify TESTKBRD. Keyboard Controller soft reset/power-on test. Programmable Interval Timer test is in progress or failed.
05 If manufacturing tests 1 through 5 are repeated over and over, **** 8042 control status. Soft reset/power-on has been determined; ROM startup is imminent. DMA first time as **** is in progress or failed.
06 Initialize circuit boards for ****, deactivate video, parity, and DMA circuit boards, as well as clear DMA circuit boards, all page registers, and CMOS shutdown bytes. Booted ROM Calculated ROM BIOS check sum, and Checked keyboard buffer clear. The DMA initial page register read/write test is in progress or failed.
07 Processor Test 2, verify CPU registers are working. ROM BIOS check sums are normal, the keyboard buffer is cleared, and a BAT (Basic Assurance Test) command is issued to the keyboard.
08 Initialize CMOS timers***, normal update timer cycle. A BAT command has been issued to the keypad and a BAT command is about to be written. RAM update check is in progress or failed.
09 EPROM checks sum and must equal zero to pass. Verifying basic assurance tests for the keyboard, followed by verification of keyboard command bytes. The first 64K RAM test is in progress.
0A Initializing the video interface***. Keypad command byte code issued, about to write command byte data. The first 64K RAM chip or data line has failed and shifted.
0B Test 8254 channel 0. Write keyboard controller command byte, about to issue blocking/unblocking commands for pins 23 and 24. The first 64K RAM odd/even logic fails.
0C Testing 8254 channel 1. Keyboard controller pins 23 and 24 blocked/unblocked; NOP command issued. Address line failure on first 64K RAN.
0D 1. Check that the CPU speed matches the system clock. 2. Check that the control chip has been programmed with a value that matches the initial setting. 3. Video channel test; if it fails, sound the horn. The NOP command has been processed; then test the CMOS stop-open register. Parity failure of the first 64K RAM
0E Test CMOS stop byte. CMOS stop-open register read/write test; will calculate CMOS check sum. Initialize input/output port addresses.
0F Test extended CMOS: CMOS check sum has been calculated Write diagnostic byte; CMOS starts initial ****. (Article source: /dnwxld/creat/blog/)
10 Testing DMA channel 0. CMOS has initialized***; CMOS status register is about to initialize*** for date and time. The first 64K RAM bit 0 is faulty.
11 Testing DMA channel 1. CMOS status register is initialized***, about to disable DMA and interrupt controller. The first 64DK RAM bit 1 has failed.
12 Testing the DMA page register. Disabled DMA controller 1 and interrupt controllers 1 and 2; about to video display and initialize port B***. The first 64DK RAM bit 2 is faulty.
13 Testing the 8741 keyboard controller interface. Video display is deactivated and port B is initialized***; about to start circuit chip initialization/memory auto-detect. The first 64DK RAM bit 3 is faulty.
14 Test memory update trigger circuit. End of chip initialization/memory autodetect; 8254 timer test about to begin. First 64DK RAM bit 4 fault.
15 Testing the opening 64K of system memory. Channel 2 timer halfway through test; 8254 channel 2 timer about to complete test. First 64DK RAM bit 5 failed.
16 Building the interrupt vector table used by the 8259. Channel 2 timer test finished; 8254 channel 1 timer about to complete test. First 64DK RAM bit 6 fault.
17 Calibrate video I/O operation, enable video BIOS if equipped. Channel 1 timer test completed; 8254 channel 0 timer about to complete test. First 64DK RAM bit 7 failure.
18 Test video memory, if installing the selected video BIOS passes, by can be bypassed. Channel 0 timer test completed; about to start updating memory. First 64DK RAM bit 8 fault.
19 Testing channel 1 interrupt controller (8259) mask bit. Memory update has begun; memory update will then be completed. First 64DK RAM bit 9 fault.
1A Tested the interrupt controller (8259) mask bit on channel 2. The memory update line is being triggered and is about to check the 15 microsecond on/off time. First 64DK RAM bit 10 fault.
1B Testing CMOS battery level. Completed memory update time 30 microsecond test; about to start basic 64K memory test. First 64DK RAM bit 11 fault.
1C Test CMOS check sum. . First 64DK RAM bit 12 fault.
1D Tuning CMOS configuration. . First 64DK RAM bit 13 fault.
1E Determine the size of the system memory and compare it to the CMOS value. . First 64DK RAM bit 14 fault.
1F Test 64K memory to ****640K. . First 64DK RAM bit 15 fault.
20 Measure fixed 8259 interrupt bits. Starting basic 64K memory test; about to test address lines. Slave DMA register test in progress or failed.
21 Holding non-maskable interrupt (NMI) bit (parity or input/output channel check). Passing address line test; parity about to be triggered. Main DMA register test in progress or failed.
22 Testing the interrupt function of the 8259. End of triggered parity; will start serial data read/write test. Main interrupt mask register test is in progress or failed.
23 Tests protection methods 8086 virtual and 8086 page. Basic 64K serial data read/write test is working; about to start any conditioning before interrupt vector initialization. Slave Interrupt Masked Memory tests are in progress or failing.
24 Determination of 1MB or more of extended memory. Any adjustments prior to vector initialization are complete and interrupt vector initialization is about to begin***. Setting the ES segment address register register to the high end of memory.
25 Tests all memories after the first 64K. Completes interrupt vector initial ***; will start reading out the 8042's input/output ports for *** style interruptions. Load interrupt vector is in progress or failed.
26 Test protection mode exception. Read out the 8042's input/output ports; about to start for *** style interrupt to make global data for initial ***. Turn on the A20 address line; make it participate in addressing.
27 Determine the control or mask RAM for the ultra cache memory. The all 1 data initial **** is finished; any initial **** after the interrupt vector will follow. Keypad controller tests are in progress or failing.
28 Determine the control or special 8042 keyboard controller for the hyper cache memory. Completing initial **** after interrupt vector; about to tune monochrome mode. CMOS power failure/check sum calculations are in progress.
29 . Monochrome mode has been tuned; color mode is about to be tuned. CMOS configuration validity check is in progress.
2A Initializing the keyboard controller***. The color mode has been tuned, and the trigger parity before ROM test is about to be performed. Empty 64K of base memory.
2B Initialize disk drives and controllers***. Trigger parity is over; about to control any adjustments required before the optional video ROM check. Screen memory test in progress or out of order.
2C Check serial port and make initial ****. Completing processing prior to video ROM control; about to view any selected video ROM and control it. Screen initial *** is in progress or failed.
2D Detecting the parallel port and initializing it***. Control of any selected video ROM has been completed and control of any other processing after control of the video ROM reply is about to be performed. The screen sweepback test is in progress or failed.
2E Initializing hard disk drives and controllers***. Recover from processing after video ROM control; if EGA/VGA is not detected perform monitor memory read/write test. Detection of video ROM is in progress.
2F Math coprocessor detected and initialized***. No EGA/VGA detected; a display memory read/write test is about to begin.
30 Building base and extended memory. Passed display memory read/write test; about to do a scan check. Consider the screen to be working.
31 Tests selected ROM from C800:0 to EFFF:0 and makes initial ****. The monitor memory read/write test or scan check failed and another monitor memory read/write test is about to be performed. The monochrome monitor is working.
32 Program the I/O chips such as COM/LTP/FDD/Sound device on the motherboard to fit the set values. Read/write test through another monitor memory; yet another monitor scanning check will be performed. The color monitor (40 columns) is working.
33 . The video monitor check is complete; the monitor off type will begin to be verified using the adjustment switches and the actual **** card. The color monitor (80 columns) is operational.
34 . The monitor adapter has been verified; the display will then be adjusted. Timer ticking interrupts the test is in progress or malfunctioning.
35 . Finished tuning the display; about to check the BIOS ROM data area. Stop test is in progress or malfunctioning.
36 . Checked BIOS ROM data area; about to tune cursor for power-on information. A-20 in the gate circuit is out of order.
37 . Cursor tuning for recognizing power-on information has been completed; power-on information is about to be displayed. Unexpected interruption in the protection mode.
38 . Completion of display of energization information; about to read out new cursor position. RAM test in progress or address fault > FFFFH.
39 . Saved cursor position read; about to display reference information string.
3A . End of reference information string display; discovery information about to be displayed. Interval timer channel 2 tested or failed.
3B Initializing auxiliary ultra cache memory with OPTI circuit chip (just 486) ***. Discovery
3C Flags to allow **** CMOS settings are established. . Serial port test is in progress or malfunctioning.
3D Initializing keyboard/PS2 mouse/PNP device and total memory node. . Parallel port test is in progress or failed.
3E Attempting to open L2 cache. Math coprocessor tests are in progress or failing.
40 . Started ***Virtual mode test; about to test from video memory. *** CPU speed to precisely match peripheral clock.
41 Interrupts have been turned on and data will be initialized for 0:0 detection of memory transformations (interrupt controller or bad memory) Recovery after verification from video memory; *** Descriptor table soon. System ***Part board selection failure.
42 Display window ***SETUP: Descriptor table is ****ed; virtual memory test is about to be performed. Extended CMOS RAM failure.
43 Serial and parallel port initialization if it is ready*** for BIOS. *** Virtual mode; about to implement interrupts for diagnostic mode. .
44 . BIOS interrupts are initialized.
45 Initializing the math coprocessor. Data is initialized***; about to check memory at 0:0 return as well as find out the size of the system memory.
.46 . Test memory has returned; memory size has been calculated and pages are about to be written to test memory. Check the read-only memory ROM version.
47 . About to test write page in extended memory; about to write page in base 640K memory. .
48 . Basic memory has been written to the page; about to finalize 1MB or more memory. Video check, CMOS reconfiguration.
49 . Memory below 1BM identified and examined; about to identify memory above 1MB. ...
4A . Locate memory above 1MB and verify; about to check BIOS ROM data area. Perform video initialization.
4B . End of BIOS ROM data area verification; about to check
4C . Clearing more than 1MB of memory (soft reset) About to clear more than 1MB of memory . Mask video BIOS ROM. .
4D Memory over 1MB cleared (soft reset); will save the size of the memory. .
4E If an error is detected; displays the error message on the display and waits for the customer to press
4F Reads and writes soft and hard disk data for DOS boot. Starts displaying the size of the memory, being tested memory will bring it up to date; serial and random memory tests will be performed. .
50 Stores the CMOS value in the current BIOS supervisory time zone into CMOS. Completes memory tests up to 1MB; will size high-speed memory for relocation and masking. Send the CPU type and speed to the screen.
51 . Tests memory above 1MB. .
52 All ISA read-only memory ROMs are initialized, and eventually initialization such as assigning IRQ numbers to the PCI. Completed testing of 1MB or more of memory; about to *** return to real-address mode. *** Keyboard testing.
53 Initialize the serial and parallel ports and set the values of the time types if it is not a ready*** to use BIOS. Saves the size of CPU registers and memory, which will *** real-address mode. .
54 . Successfully turns on the real-address mode; about to recover **** the registers saved at shutdown. Scanning the "strike key"
55 . Registers recovered; will deactivate the address lines of gate circuit A-20. .
56 . Successfully deactivated the address line of A-20; about to check the BIOS ROM data area. End of keyboard test.
57 . Halfway through checking the BIOS ROM data area; proceeding .
58 . End of BIOS ROM data area check; will clear the Found
59 . The ＜ESC＞ message has been cleared; the message is displayed; the DMA and interrupt controller test will begin soon. .
5A . . Pressing the "F2" key to make settings is displayed.
5B . . Test the base memory address.
5C . . Test the 640K base memory.
60 Setting up hard disk boot sector virus protection. Passing the DMA page register test; about to test video memory. Testing extended memory.
61 Displaying the system configuration table. End of video memory verification; about to test DMA #1 base registers. .
62 Starting system boot with interrupt 19H. Passing DMA #1 base register test; DMA #2 register test forthcoming. Testing extended memory address lines.
63 . Passing the DMA #2 base register test; about to check the BIOS ROM data area. .
64 . Halfway through the BIOS ROM data area check; proceeding .
65 . BIOS ROM data area check is over; will program DMA devices 1 and 2. .
66 . End of DMA device 1 and 2 programming; about to use interrupt controller 59 for initial ****. Cache registry is optimally configured.
67 . Initial 8259 *** is finished; about to start keyboard test. .
68 . . Making both external Cache and internal CPU Cache work.
6A . . Test and display the external Cache value.
6C . . Display blocked content.
6E . . Display subordinate configuration information.
70 . . Detected error codes are sent to the screen display.
72 . . Detect if there is an error in the configuration.
74 . . Test the real-time clock.
76 . . Scan for keyboard errors.
7A . . Locking the keyboard.
7C . . Set hardware interrupt vector.
7E . . Test for an installed math processor.
80 . Keyboard test started. is clearing and checking for stuck keys. about to bring the keyboard back up. Turns off programmable input/output devices.
81 . Finding the wrong stuck key for keyboard recovery; about to issue a test command for the keyboard control port. .
82 . End of keyboard controller port test; about to write the command byte and make the circular buffer for initial ****. Testing and installing the fixed RS232 interface (serial port).
83 . Command bytes have been written and initial **** of global data has been completed; about to check that there are no keys locked. .
84 . Have checked for locked keys; about to check for memory mismatch with CMOS. Detecting and installing fixed parallel ports.
85 . Have checked the size of the memory; about to display soft errors and password or bypass arrangements. .
86 . The mnemonic has been checked; programming before bypass arrangement is about to take place. Reopen programmable I/O devices and detect fixed I/O for conflicts.
87 . Pre-arrangement programming completed; CMOS arrangement programming will be performed....
88 . Clears the screen from CMOS arrangement program recovery; later programming will be performed. Initialize the BIOS data area.
89 . Completing post-schedule programming; about to display power-on screen information. .
8A . Displaying the first screen message. Perform extended BIOS data area initialization.
8B . Displays the message: about to block the primary and video BIOS. .
8C . Successful masking of the primary and video BIOS will begin the programming of the post-CMOS arrangement option. Perform floppy drive controller initialization.
8D . Already arranged any option programming, then check the slide up the mouse and carry out the initial ****.
8E . The mouse has been checked and the initial **** has been completed; the hard and soft disks are about to be reset.
8F . The floppy disk was checked; the disk will be initially ****ed and subsequently equipped with a floppy disk....
90 . End of floppy disk configuration; the presence of the hard disk will be tested. The hard disk controller is initialized.
91 . Hard disk presence test ends; the hard disk is then configured. The local bus hard disk controller initializes.
92 . Hard disk configuration complete; about to check BIOS ROM data area. Jump to user path 2.
93 . BIOS ROM data area half checked; proceeding. .
94 . The data area of the BIOS ROM is checked, i.e., the size of the basic and extended memory is adjusted. Close the A-20 address line.
95 . Memory size is adjusted for mouse and hard disk Type 47 support; display memory is about to be examined.
96 . Recover after checking the display memory; about to perform the initial **** before the C800:0 optional ROM control. The "ES segment" register is cleared.
97 . End of any initial **** prior to C800:0 optional ROM control, followed by optional ROM check and control....
98 . Control of the optional ROM is complete; any processing required after control of the optional ROM reply is about to be performed. Find ROM selection.
99 . End of any initial **** required after the optional ROM test; about to establish the timer's data area or printer base address. .
9A . Return *** action after the timer and printer base address have been set; i.e., the RS-232 base address is set. Mask ROM selection.
9B . Return after RS-232 base address; i.e., about to perform initial **** for coprocessor test.
9C . End of initial **** required before coprocessor test; coprocessor initial **** to follow. Establish power conservation management.
9D . The coprocessor is ready for initial ****, and any initial **** after the coprocessor test is about to be performed .
9E . Completing the initial **** after the coprocessor will check the extended keyboard, keyboard identifier, and numeric lock. Open hardware interrupts.
9F . The extended keypad has been checked, the tuning identifier, and the numeric lock is on or off, and the keypad identification command will be issued....
A0 . A keypad identification command is issued; i.e., the keypad identification flag will be restored. Set the time and date.
A1 . Keyboard recognition flag restored; followed by cache memory test. .
A2 . Cache memory test completed; about to display any soft errors. Check the keyboard lock.
A3 . End of soft error display; about to adjust the rate of keyboard strikes. .
A4 . The rate of keyboard strikes is tuned; the wait state of the memory is about to be formulated. Initialization of the keyboard repeat input rate.
A5 . The memory wait state is formulated; the screen will then be cleared .
A6 . Screen cleared; parity and unmaskable interrupts will be initiated soon. .
A7 . Non-maskable interrupts and parity are enabled; any initial **** required to control the optional ROM at E000:0 is about to be performed...
A8 .
A8 . The initial **** before E000:0 is finished, and then any initial **** after E000:0 will be controlled. Clear the "F2" key prompt.
A9 . Return from Control E000:0 ROM, about to perform any initial **** required after Control E000:0 optional ROM.
AA . End of initial **** after Control E000:0 Optional ROM; system configuration about to be displayed. Scanning the "F2" key strikes.
AC . . *** Settings .
AE . . Clear power-on self-test flag.
B0 . . Check for non-critical errors.
B2 . . Power-on self-test complete ********* for system boot.
B4 . . The buzzer sounds once.
B6 . . Detect password setting (optional).
B8 . . Clear all description tables.
BC . . Clear checksum check value.
BE Program Defaults*** control chip that conforms to the modulatable binary defaults table. . Clear screen (optional).
BF Test CMOS build value. . Detect virus, prompt to do data backup.
C0 Initialize cache. . Try boot with interrupt 19.
C1 Memory self-test. . Look for "55" and "AA" flags in the boot sector.
C3 First 256K memory test. . .
C5 Copy BIOS from ROM for quick self-test. . .
C6 Cache self-test. . .
CA Detects Micronies overrun buffer memory (if present) and initializes it***. . .
CC Turn off the non-maskable interrupt processor. . .
EE Unexpected exceptions to the processor. . .
FF Give INI19 guide to load the program control, the motherboard OK.
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