When doing FPGA-based time interval measurement, why is it said that the clock frequency is 100MHZ, so the maximum deviation is 10ns, and what is the relationship between clock frequency and error?

In FGPA, the time interval measurement uses the rising edge (or falling edge) of the clock as the trigger signal for the counter, and the interval between clock edges is 10ns, so the maximum deviation is 10ns.

The higher the clock frequency, the higher the accuracy. If you want to increase the accuracy, you can only increase the clock frequency