1. Functional design stage.
Designers should set some specifications for the application of products, such as functions, operating speed, interface specifications, ambient temperature, power consumption, etc., as the basis for future circuit design. We can further plan how to divide software modules and hardware modules, which functions should be integrated in SOC and which functions can be designed on the circuit board.
2. Design Description and Behavior Level Verification
After the function design is completed, the SOC can be divided into several functional modules according to the function, and the IP core to be used to realize these functions can be determined. This stage will affect the internal architecture of SOC and the interaction between modules.
Dynamic signals and the reliability of future products. After the module is determined, the design of each module can be realized by hardware description language such as VHDL or Verilog. Then, the circuit simulator of VHDL or Verilog is used to verify the design through functional simulation or behavior simulation. Note that this functional simulation does not consider the actual delay of the circuit, but it cannot obtain accurate results.
3. Logical synthesis
After the design description is confirmed to be correct, it can be synthesized with a logic synthesizer. In the process of synthesis, it is necessary to select the appropriate logic cell library as the reference of the integrated logic circuit. The writing style of hardware language design description file is an important factor to determine the execution efficiency of comprehensive tools. In fact, the HDL grammars supported by the integration tools are limited, and some over-abstract grammars are only suitable as simulation models for system evaluation, which is unacceptable to the integration tools. The gate-level netlist is obtained through logical synthesis.
4. Gate-level netlist verification.
Gate level function verification is register transfer level verification. The main task is to confirm whether the integrated circuit meets the functional requirements, which is generally completed by the gate-level verification tool. Please note that the delay of gate circuit needs to be considered in this simulation stage.
5. Layout and wiring
Layout refers to arranging the designed functional modules on the chip reasonably and planning their positions. Wiring refers to the wiring that completes the interconnection between modules. Note that the wiring between modules is usually long, so the delay will seriously affect the performance of SOC, especially above the 0.25 micron process.