sram is the abbreviation of English static ram, it is a kind of memory with static access function, it does not need to refresh the circuit that can save the data stored inside it.
Basic introduction Chinese name ：SRA memory Foreign name ：SRANM Host board operation, host board basic design, selection, market seeking change new, host board operation Operation of the completed sram memory host board. Boot in msdos mode and try to perform data read/write operations starting from d0000h using the debug instruction. If it is confirmed that the motherboard is able to operate normally, supply power to each copy of the power connector (2), de-energizing the personal computer, with a loss current of about 40 μa. Restart the ms-dos mode and read the address of the person who just wrote it, because it is possible to read the data written by the person, and thus it can be seen that each copy of the power supply is playing a corresponding role. Since the field from d0000h is the extended bios field of the pc/at, data such as additional header information will be recalled before the operating system is started if it is written on the sram. Experiment with various carefully researched programs installed on the sram, and you will make very interesting discoveries. sram, unlike flash memory, etc., is very simple to replace, and can be replaced in 1-bit byte increments, with no replacement time required. Once the battery is removed the data will be lost, thus allowing a wide variety of experiments to be carried out in the phase prior to the implementation of romization, which is its convenience. Basic design of the main board Address buffer A buffer is added to the sa0 to sa15 addresses supplied to the memory. The buffer is also possible by utilizing the 74ls244, but it can be used in one direction through the 74ls245 because of the simplicity of the 741ls245 wiring. The data buffer is to be received utilizing the 74ls245 because the data needs to be carried out in both directions. Leave the gate open all the time and control the direction by reading signals to the memory. This time we use the method of setting the read signal of the memory on the pld to output only when cs1 is valid. The pld (memdec) pld set is used to generate the chip select, de, and we signals to the memory. The chip select signal is selected outside the refresh cycle when the address high bit (sa16 to sa19) is dh (set d0000h to dffffh in the sram host board space) and bale is low. Set the memory read/write signals to be output when chip select and *** emr/ *** emw are active. Switching of power supply for each copy The focus of each copy of the battery is on power switching and control of the chip select signal. This time, for simplicity, simply get the diode OR of v and the battery (a 3.6v battery is provided for 2), but attention needs to be paid to the diode forward voltage drop. If the supply voltage is much lower than the supplied voltage, it may happen that the operating voltage is exceeded or that the input pins have a higher voltage than the supply voltage. Chip select control For battery backup, the chip select signal of the memory must be disabled. This time, although we will only utilize ce1 for control, it is necessary to make ce1 maintainable at a value similar to the supply voltage (v-0.2v or more for the cy62l28) in order to keep the loss current low. In order to perform chip select control, the circuit will be composed of an adm708 (analog device) as a power supply monitoring ic and a cmos gate of the 74hc series. the adm708 is originally a device used by the cpu to generate a reset signal, and there are several types of this ic used for power supply monitoring, including power switching circuits used for each portion of the battery of the sram, and an ic that has built-in chip select control. the circuit will make use of this type of ic. The circuitry of this kind of ic is very simple, but the price of the device is a bit high, which is its disadvantage.The pinout and internal block diagram of the adm708 that we utilize this time is shown in Figure 1. The key to switching the power supply is how far the supply voltage drops to make it so that it becomes ignoring the various states of the host signals, and it is quite cumbersome to have such control by individual components.
Figure 1 adm708 pin configuration and block diagram
From the block diagram can be understood, adm708 internal with each 4.40v and 1.25v generation circuit, 4.40v generation circuit and v compared to the increase of a reset generation circuit. When the supply voltage is below 4.40v, the reset/reset signal is active (reset is high, reset is low). The operation of the circuit is shown in Figure 2. Since v itself will gradually decrease and the output voltage on the reset side will also decrease piece by piece, for this reason we will utilize the output of reset this time. When the supply voltage is out of the operating range of the adm708, a pull-down resistor is added to ensure a low level, which is accepted by the gate of the Schmitt flip-flop of the 74hc14. The power supply pins of the 74hc14, and in the next stage the 74hc32, are common to the power supply pins of the sram.
Figure 2 Operation of the Backup Circuit Thus, if the reset of the adm708 is low, the output pin of the 74hc32 is forced high, and because the sram's ce1 is invalid, it becomes standby. Selection sram (static random access memory) is a memory device capable of storing data as long as it is powered and is a key part of most high-performance systems. sram has a multitude of architectures, each targeting a specific set of applications. The purpose of this paper is to provide a comprehensive review of the srams currently available on the market, and to briefly explain which type of sram is the best choice for a particular application. At a high level, srams can be divided into two broad categories: synchronous and asynchronous. Synchronous srams use a single input clock to initiate all transactions to memory (reads, writes, unselects, etc.). Asynchronous srams, on the other hand, do not have a clock input and must monitor inputs for commands from the controller. Once a command is recognized, the devices will execute it immediately. Synchronous sram family classification The selection of the best sram for a particular application depends on a number of factors, including power constraints, bandwidth requirements, density, and read/write modes of operation. There are a variety of synchronous and asynchronous srams available to meet different system requirements, and each will be described in this article. Comparison of various synchronous sram synchronous sram in the last century, the late 80's the first time on the market, initially for the very high performance of workstations and servers in the second level (l2) cache memory sets. After the mid-1990s, it found its place in more mainstream applications, including second-level cache memory in personal computers. Since then, synchronous srams have been prevalent in the design of many applications, including high-performance networks (where they are commonly used for data buffers, cache, queue management functions, and statistics buffers). Synchronous srams are available in a variety of architectures. The following is a brief description of some of the "mainstream" devices. 1: Standard Synchronous Srams Standard synchronous srams are the first type of synchronous srams accepted by the "mainstream suite", although these devices are primarily oriented towards the pc l2 cache memory suite. Although these devices are mainly for pc l2 cache memory suite, but also penetrated into the non-pc suite of areas, such as network, telecommunications, digital signal processing (dsp), as well as medical and test equipment. The standard synchronous sram has two basic formats: pipelined and passthrough. The difference between the two is that straight-through srams only have registers on the inputs, and when address and control inputs are captured and a read-access operation is initiated, the data is allowed to "stream" directly to the outputs. Straight-through architectures are often preferred when initial latency is more important than sustained bandwidth. A "pipelined" synchronous sram has both an input register and an output register. The operating frequency and bandwidth offered by a pipelined sram is usually higher than that offered by a straight-through sram, and therefore a pipelined sram is often preferred when a higher bandwidth is required and the initial latency is not very sensitive. 2: Nobltm (no sink latency) srams do not allow for a "wait state" for some implementations. Some sets do not allow "wait states". For example, a "wait state" in a network application can have a serious impact on performance. To address this issue, Cypress has introduced no-bleed-latency (nobl) type srams, which are similar to standard synchronous srams but have additional on-chip logic circuitry designed to completely eliminate the "wait states" required by the standard synchronous sram family. By eliminating these "wait states", these srams are able to achieve 100] bus utilization (independent of read/write mode). This feature greatly improves memory performance, especially when there are frequent read/write transitions. nobl srams are also available in two versions: straight-through and pipelined. Straight-through nobl srams always have a single-cycle offset, while nobl pipelined srams maintain a two-cycle offset.3: Quadruple Data Rate (qdrtm) SramsDespite the introduction of nobl architectures and performance improvements over standard synchronous srams, some systems demanded more performance. Therefore, Cypress, renesas, idt, nec and samsung and several other companies jointly developed the qdr type sram. qdr architecture is designed to meet the requirements of those who require low latency and the required bandwidth is significantly higher than the nobl type architecture to provide the ability of the "high bandwidth demand type" system needs. One of the most significant differences between qdr-based srams and nobl-based srams is the separation of the read and write ports. These ports operate independently and support parallel read and write transactions. qdr-type srams are capable of supporting two simultaneous transactions at the ddr transfer rate (2x), hence the name quadruple data rate (qdr). qdr-type srams are available in two basic types: 2-word bursts and 4-word bursts. The difference between these two types is the length of the burst supported during each transaction.4: qdr-ii type sramqdr- ii type sram is similar to the qdr type sram, but with a further improvement in performance. Compared to a qdr-type device of the same frequency, the total data effective window area generated by the qdr-ii type sram is about 35] larger. In addition, the qdr-ii type sram products also have one and a half more delay cycles than the qdr type devices. This additional half clock cycle provides much higher frequency and bandwidth with minimal impact on initial latency. 5: ddr-type sram If qdr-type srams are geared toward applications with balanced read/write modes, ddr-type sram architectures are aimed at applications that require data streaming (e.g., multiple reads followed by multiple writes) and require much higher bandwidth than standard synchronous devices or noblocks. The ddr-type sram is designed for use in applications that require data streaming (e.g., multiple reads followed by multiple writes) and require a much higher bandwidth than a standard synchronous or nobl device. ddr-type srams maximize performance by providing superior overall bus utilization and a much higher total bandwidth. Like qdr-type srams, ddr-type srams are available in two formats: 2-word bursts and 4-word bursts. The choice depends on the granularity of the data required and the width of the data sink of the memory. Comparison of Various Asynchronous Srams The second major category of srams is the asynchronous srams. srams that do not have a clock input are asynchronous. In these devices, read and write operations are initiated as soon as the device receives an instruction. One of the biggest advantages of using asynchronous srams is that they have a decades-long history of use and are well understood. Because asynchronous srams have been on the market for so long, many standard processors include memory controllers that are already equipped with asynchronous sram interfaces, minimizing the amount of design effort required. Typical access times for asynchronous sram are 8ns (or more). Therefore, they are typically used in systems with clock frequencies of 100mhz (or less). Asynchronous srams can be further divided into two main categories: fast asynchronous srams and low-power asynchronous srams (mobltm).1: Fast Asynchronous Srams Asynchronous srams with access times of 35ns (or less) are categorized as "fast" asynchronous srams. these memories are typically used in older systems. These memories are often used in older systems with high power consumption (1/2w or more is common). Typical applications include old pc l2 cache memories, high-speed storages, and buffer memories in industrial applications.2: mobltm low-power asynchronous sram Some applications (e.g., cellular telephony) are more concerned with power consumption than with performance. As a result, manufacturers such as Cypress have introduced a family of srams with very low power consumption. Cypress's mobl (meaning "longer battery life") low-power asynchronous sram product library brings together a wide range of devices with typical access times of about 40ns (or more) that are optimized for low power consumption. Typical standby power consumption can be as low as 10μw (or less) and operating power consumption can be as low as 30mw (or less). These devices are available in memory densities ranging from 64kb to 16mb. Pseudo-sram (also known as psram) Pseudo-sram (or pseudo-psram) is a viable solution if storage densities above 16mb are required. Pseudo-sram refers to a memory device that has a drm memory core and a "sram-type" interface. Since psram uses a dram core, it also needs to be periodically refreshed in order to save data. The difference is that while standard drams have refresh control external to the device, psrams have an "implicit" refresh circuitry, which allows them to be easily used as a memory density upgrade to other asynchronous srams. Conclusion When choosing a sram, you are faced with many options. In some cases, the choices are limited. Many processors that have established themselves firmly include memory controllers that support specific sram architectures. Newer processors are designed to be more flexible. In order to determine the best available option, it is critical to prioritize the memory subsystems (i.e., megabits per second, initial latency, operating power, standby power, cost, etc.) as well as the operating characteristics of the system (read/write modes of operation, operating frequency, etc.). The net suite tends to have a read/write mode close to 50/50, which is appropriate for solutions using the qdr family. Other suites (even functional circuits within the same system) tend to have unbalanced read/write modes, which lends itself to the use of public **** i/o architectures, including standard synchronous, nobl, and ddr types. Some other systems require the lowest possible power consumption, in order to extend battery life, optional programs are mobl-type sram and psram. The market for new static random access memory (sram) has been widely used in a variety of occasions over the years. Where the need for fast access to data sets, especially in the case of the requirement of the initial access waiting time is very short, will consider the use of sram, which has become a common sense. Historically the sram memory market has had a few ups and downs, and most of the time the entire market demand would skyrocket for a new sram suite. For example, in 1995 when pc's were growing rapidly, sram served as a cache for cpu's, and thus its demand grew dramatically. the same thing happened to the sram memory market in 1999 with the net market, and in 2003 with the explosion of the cell phone market. However, in the past few years, the sram memory market has shrunk dramatically due to various reasons. Market research data shows that the sram memory market capacity has shrunk from $6 billion in 2000 to $1 billion at present. The shrinking market volume has also led to changes in the vendor landscape, limiting the potential for revenue growth in the sram segment of leading vendors. Many of these vendors are multi-billion dollar companies that are more interested in products with greater market capacity. Over the past 2 or 3 years, we have seen Micron, Motorola, ibm, Toshiba, Samsung, nec, and Renesas exit the sram memory market in whole or in part. Based on this status quo, people can't help but ask: will sram completely die? We believe that the answer is no. From a technical point of view, compared with competing technologies (such as sdram and even rldram), sram still has the shortest initial access wait time. Other products hardly have initial access wait times of less than five cycles, and waits of more than three cycles are unacceptable in many of the typical implementations of sram, especially in the network and telecom implementations. On the other hand, due to the high cost of re-designing systems, many older designs are still using sram and will continue to do so for quite some time. Over the past few years, sram vendors have also developed a number of different types of srams for different applications; for example, high-end networking equipment requires very high-speed synchronous srams to provide g-level bandwidth for various systems. We believe that high-speed and ultra-high-speed srams will continue to evolve in the future. This is driven by the continued demand for higher frequency synchronous srams in the telecom suite. Clock speeds have increased from 66mhz to 300mhz. in order to provide customers with more bandwidth, synchronous sram has resulted in a number of different architectures, including nobl (no sink wait time), qdr (quadruple data rate), qdrii, and now qdrii+. As the market leader in sram memory, Cypress initiated the creation of the qdr consortium and has been a member from the beginning. Cypress was also the first to offer 72m sync/nobl and qdr srams, which are the largest srams in the world. srams have become an important support component in high-end networking systems as the drive for bandwidth and speed continues. another branch of srams is asynchronous srams, which do not rely on a clock to output data, as synchronous srams do. This type of sram does not rely on the clock to output data as synchronous srams do, but guarantees to read and write data/data at a specific time. The oldest generation of srams is the fast asynchronous srams, with speeds generally ranging from 10ns to 20ns. these srams are widely used in dsl, ip telephones, bts, voip, switches, medical systems, printing/fax machines, car navigation systems, etc. The top suppliers of fast asynchronous srams are the most widely used in the industry. Top suppliers of fast asynchronous srams include Cypress, Samsung and Renesas. However, as part of its "longevity" strategy, only Cypress has maintained the broadest product line. Cypress still supplies customers with 4kb sram, which went into production 20 years ago. Another branch of asynchronous srams is the low-power srams, which typically have low access speeds, taa of 55ns or 70ns. these srams minimize power consumption, especially standby current (i *** 1, i *** 2), to meet the requirements of mobile devices. Typical i can reach 1ma and i *** 1/i *** 2 down to 1ua level. This type of memory has a wide range of applications in cell phones, consumer electronics, automobiles, POS, printers, medical devices and other fields. Among the various low-power sram memory markets, Cypress's mobltm (longer battery life) sram stands out for its ability to achieve 45ns TAA while maintaining the lowest i *** 2. Among the top three micro-power sram suppliers, Samsung recently withdrew from the market. Renesas still maintains existing product offerings, but there is no indication that they will expand their current product line. The only supplier still developing new products on newer technology platforms is Cypress, and still maintains the widest product line in the space, making Cypress the only tier 1 supplier in these segments and triggering a reshuffling of the market over the past few quarters. We expect out-of-stocks and price increases to benefit second-tier suppliers and spawn new players in the asynchronous sram memory market. However, it will still be an uphill battle for second-tier and new suppliers, as the memory business requires scale and a long learning experience. On the other hand, customers are aggressively moving to new technologies as Cypress suites 90nm technology for micro-power sram. For new customers, this is actually a good opportunity to adopt Cypress's 90nm technology directly and enjoy its capacity and cost advantages.