A/D and D/A converters are widely used in detection and control devices such as processes, instruments and equipment. With the development of large-scale integrated circuit technology, various high-precision, low-power, programmable and low-cost A/D converters are constantly introduced, which makes the circuit of microcomputer control system more concise and reliable.
The connection between TLC2543 and peripheral circuits is simple, and the three control inputs are CS (chip selection), I/O clock and serial data input respectively. On-chip 14-channel multiplexer can select 1 1 input or any of three internal self-test voltages. Sample-and-hold is automatic, and EOC output becomes high level after conversion.
The main features of TLC2543 are as follows:
11analog input channels;
● Sampling rate of ●66ksps;
● The maximum conversion time is10 μ s;
●SPI serial interface;
● The maximum linear error is1LSB;
Low power supply current (typical1ma);
Low power-down mode current is 4 μ A. ..
2.TLC2543 pin function and interface timing
2. 1 TLC2543 pin arrangement
The pin arrangement of TLC2543 is shown in figure 1. The pin function is described as follows:
Ain0 ~ ain 10: analog input, selected by internal multiplexer. For 4. 1MHz I/O clock, the driving source impedance must be less than or equal to 50 Ω;
CS: chip selection terminal. Changing CS from high level to low level will reset the internal counter and control and enable data output, data input and I/O clock. When CS changes from low to high, data input and I/O clock will be prohibited within the set time;
Data input: serial data input. Serial data starts with MSB, and moves into 4-bit address at the first 4 rising edges of I/O clock, which is used to select the next analog input signal or test voltage to be converted, and then I/O clock inputs the remaining bits in turn;
Data output: three-state output end of A/D conversion result. When CS is high, this pin is in high impedance state; When CS is low, this pin is set to the corresponding logic level from the MSB value of the previous conversion result; EOC: end of conversion. After the falling edge of the last I/O clock, EOC changes from high level to low level and remains until the conversion is completed and the data is ready for transmission.
And: positive terminal of power supply and grounding;
Ref+, ref-: positive and negative reference terminals. Usually ref+ is connected to VCC and ref- is connected to GND. The maximum input voltage range depends on the voltage difference between the two ends;
I/O clock: clock input/output terminal.
2.2 working sequence of TLC 2543
TLC2543 uses 16 clock cycles for each conversion and data transmission, and the timing of CS is inserted between each transmission cycle. The time sequence is shown in Figure 2.
As can be seen from the timing diagram, when CS of TLC2543 becomes low level, the conversion and transmission process begins. The first eight rising edges of the I/O clock key eight input data bits into the input data register, and at the same time, it moves the remaining 1 1 of the previously converted data out of the data output pin. When the I/O clock falls, the data changes. When CS is high, I/O clock and data input are disabled, and data output is high impedance state.
3. Connection between 3.TLC 2543 and 80C3 1
3. 1 hardware interface
Because MCS-5 1 series single-chip microcomputer has no SPI or interface with the same ability, in order to facilitate the interface with TLC2543, software is used to synthesize SPI operation, and in order to reduce the influence of microprocessor clock frequency on data transmission speed, a higher clock frequency is selected as much as possible. The interface circuit is shown in Figure 3.
I/O clock, data input and chip selection signal of TLC2543 are provided by P 1.0, P 1.6, P 1.3, and the conversion result is read by P 1.2.
3.2 interface program
Let the channel/mode control word be stored in R4, and the program will send the channel/mode control word to TLC2543 while reading the previous conversion result, and the conversion result will be stored in the memory of the adjacent address. The memory address is from 30h to 45h, with the high byte in front and the low byte in the back.
ORG 100H
Start: MOV SP, # 50H stack pointer initialization
MOV P 1, # 04HP 1 Pin Initialization
CLR P 1.0
SETB P 1.3
ACALL TLC2543
Telephone shop
JMP starting point
R4 MOV A area
CLR P 1.3
JB ACC. 1, LSB If the bit 1 of A is 1, make the low-order byte first.
MSB: MOV R5，#08
LOOP 1: MOV C，p 1.2； Data bit is read into carry bit RLC A.
MOV P 1. 1，C； Output mode/channel bit
SETB p 1.0； Generate I/O clock
CLR P 1.0
DJNZ R5，loop 1； Input/output another bit
MOV·R2； The high byte enters R2.
R4 MOV
JB ACC. 1, returns
Least significant bit: MOV R5, #08
Second loop: MOV C, P 1.2
RLC A
C MOV p 1. 1
SETB P 1.0
CLR P 1.0
DJNZ R5, loop 2
MOV R3，A
R4 MOV
JB ACC. 1，MSB
Return: RET
Store: R4 MOV A
ANL A，#0F0H
Exchange a
MOV B, No.02
MUL AB
Add one, #030H
MOV R 1，A
R2 MOV
MOV @R 1，A
INC R 1
MOV A，R3
MOV @R 1，A
Soak in water to soften
end
The above program synthesizes SPI function by accumulator and instruction with left circular shift with carry, and reads the first bit of the first byte of the conversion result into the carry (c) bit. The accumulator contents are shifted to the left by the carry bit, and the first bit of channel selection and mode data is output by P 1. 1. Then, P 1.0 changes from high level to low level to provide a serial clock. This sequence is repeated 7 times to complete the transmission of the first byte of the converted data. The second byte is transmitted by repeating the entire clock pulse and data transmission sequence 8 times.