Based on the growth method can be divided into two categories of epitaxial process (Table 1): full epitaxy (Blanket Epi) and selective epitaxy (Selective Epi, abbreviated as SEG). Process gases commonly used in three silicon-containing gas source: silane (SiH4), dichlorosilane (SiH2Cl2, referred to as DCS) and trichlorosilane (SiHCl3, referred to as TCS); some special epitaxial process should also be used in the Ge and C-containing gases germanium alkane (GeH4) and methylsilane (SiH3CH3); selective epitaxial process also need to be used to the etching gas hydrogen chloride ( HCl), the reaction in the reaction of hydrogen chloride (HCl), hydrogen chloride (HCl). HCl), the carrier gas in the reaction is generally selected hydrogen (H2).
The realization of epitaxial selectivity is generally achieved by adjusting the size of the relative rates of epitaxial deposition and in-situ (in-situ) etching, the gas used is generally chlorine-containing (Cl) silicon source gas DCS, the use of the reaction of the Cl atom adsorption on the surface of the silicon less than oxides or nitrides to achieve the epitaxial growth of the selective; due to the absence of Cl atoms in the SiH4 and the activation of low energy. Generally, it is only used in low-temperature full epitaxial process; while another commonly used silicon source TCS has a low vapor pressure, is liquid at room temperature, and needs to be introduced into the reaction chamber by H2 bubbling, but is relatively inexpensive, and often utilizes its fast growth rate (up to 5 um/min) to grow thicker silicon epitaxial layer, which is widely used in silicon epitaxial wafer production.The lattice constants of Ge of the group IV elements ( 5.646A is the least different from the lattice constant of Si (5.431A), which makes SiGe easy to integrate with the Si process. The introduction of Ge in single-crystal Si to form a single-crystal layer of SiGe can reduce the bandgap width, increase the transistor's characteristic cut-off frequency fT (cut-off frequency), which makes it in the wireless and optical communications high-frequency devices are very wide range of applications; in addition, in the advanced CMOS integrated circuit process will also be utilized with the Ge and the lattice constant mismatch with the Si (4%) the introduction of lattice stresses To improve the mobility of electrons or holes (mobility), thereby increasing the device's operating saturation current and response speed, which is becoming a hot spot in the research of semiconductor integrated circuit process. Due to the poor electrical conductivity of intrinsic silicon, its resistivity is generally more than 200ohm-cm, usually in the epitaxial growth at the same time also need to be doped with impurity gases (dopant) to meet the electrical properties of certain devices. Impurity gases can be divided into two categories: N-type and P-type: commonly used N-type impurity gases include phosphorane (PH3) and arsenane (AsH3), while P-type is mainly borane (B2H6).
Silicon and germanium silicon epitaxial process in modern integrated circuit manufacturing is widely used, summarized mainly include:
1. Silicon substrate epitaxial: silicon wafer manufacturing in order to improve the quality of the wafer is usually epitaxial on the wafer of a layer of higher purity intrinsic silicon; or in the growth of epitaxial layer on a high-adulteration silicon substrate in order to prevent the device's latch-up (latch up) effect.
2. Hetero-junction Bipolar Transistor (HBT) base area (base) heterojunction SiGe epitaxial (Figure 1): the principle is doped in the base area of the Ge component, by reducing the width of the energy band, so that the base area of the minority from the emitting region to the base area across the barrier height is reduced to improve the emission efficiency γ, therefore, the base area of the minority from the emitting region to the base area across the barrier height is lowered, so as to increase Emission efficiency γ, thus, largely improve the current amplification factor β. In order to meet the premise of a certain amplification factor, the base region can be heavily doped, and can be made thinner, which reduces the base region of the carriers across the time to improve the device cut-off frequency fT (Cut-Off Frequency), which is precisely the heterojunction in the ultra-high-speed, ultra-high-frequency devices in the advantages of.
3. CMOS source (source) drain (drain) area selective Si/SiGe epitaxial: into the 90nm process era, with the significant reduction in the size of the IC device, the source-drain junction depth is becoming more and more shallow, the need for selective epitaxial technology (SEG) in order to thicken the source-drain electrode (elevated source/drain) to (SEG) to thicken the source-drain electrode (elevated source/drain) to serve as a sacrificial layer for the subsequent silicide reaction (Fig. 2), thereby reducing the series resistance, which has been reported to result in a 15% increase in saturation current (Idsat).
And for the 65/45nm technology process under development, some people use the PMOS source-drain etching epitaxial SiGe layer to introduce the compressive stress on the channel (compressive stress) (Figure 3), in order to improve the hole (hole) mobility (mobility), according to reports said to realize the saturation current (Idsat) 35 percent increase.
Strain silicon (strain silicon) epitaxy: In the relaxed (relaxed) SiGe layer above the epitaxy of a layer of single-crystal Si, due to the mismatch between the lattice constants of Si and SiGe, resulting in a single-crystal layer of Si subjected to the tensile stress (tensile stress) of the SiGe layer below and make the mobility of electrons (mobility) has been increased (Figure 4). Enhancement (Figure 4), which makes the NMOS in the case of maintaining the device size is unchanged saturation current (Idsat) has been increased, and the increase in Idsat means that the device response speed, this technology is becoming a national research hotspot.
Generally speaking, a complete epitaxial process consists of three parts:
First, according to the need to achieve the results of the process on the wafer pretreatment, including the removal of the surface of the natural oxide layer and the wafer surface impurities, for the heavy adulteration substrate wafers must be considered whether the need for a backseal (backseal) in order to reduce the subsequent epitaxial growth of the process of self-adulteration.
Then in the epitaxial process needs to be optimized for the program, today's advanced epitaxial equipment is generally a monolithic reaction chamber, can be heated to 1100 ° C or more within 100 seconds of the wafer, the use of advanced temperature detection devices can be processed to control the temperature deviation of 2 degrees or less, the reaction gas can be through the Mass Flow Meter (MFC) to make the flow rate to be accurately controlled. Before epitaxial deposition, H2 bake is generally required to remove the natural oxide layer and other impurities on the wafer surface in-situ to prepare a clean silicon surface for subsequent epitaxial deposition.
Finally, after the epitaxial process is completed, the performance indicators need to be evaluated. Simple performance indicators include the epitaxial layer thickness and electrical parameters, the thickness and electrical uniformity within the wafer, the repeatability between the wafer and the wafer, the number of particles, and the contamination
Finally, after the epitaxial process is completed, the performance indicators need to be evaluated. contamination)
In industrial production, the film thickness and electrical uniformity within the wafer are often required to be <1.5% (1σ), and for wafer manufacturers it is often necessary to examine the extended resistivity profile (SRP) of the epitaxial layer to determine whether contamination exists and the amount of contaminant impurities. In particular, for SiGe processes we often need to measure the Ge content and its depth distribution, and for processes with admixtures we also need to know the content and depth distribution of the admixture atoms. In addition, lattice defects (defect) is also a problem we must consider, in general, there are often four kinds of defects, including haze (haze), slip line (slip line), stacking fault (stacking fault) and puncture (spike), the existence of these defects on the performance of the device has a great impact on the device can lead to device leakage current increases or even device The presence of these defects has a great impact on the performance of the device, which can lead to increased leakage current or even complete failure of the device and become a fatal defect (killer effect). Generally speaking, the way to eliminate these defects is to check whether the reaction chamber leakage rate is low enough (<1mTorr/min), whether the process temperature distribution within the chip is uniform, whether the base of the wafer or the preparation of the wafer surface is clean, flat and so on.
After the epitaxial layer performance index test we also need to further optimize the epitaxial process to meet the specific device process requirements.
Silicon substrate epitaxy: In order to improve the quality of wafers in wafer manufacturing, it is common to epitaxialize a layer of intrinsic silicon on the wafer with higher purity, or to grow epitaxial layers on a highly adulterated silicon substrate in order to prevent the latch up effect of the device.