The SuccessiveApproximationRegister (SAR) ADC is a digital signal processing technique that achieves high-precision digital quantization by making multiple successive approximations. Specifically, a SARADC implements the conversion through a series of comparisons and binary bit shifts. First, the SARADC compares the input signal to an intermediate voltage value and determines whether the highest significant bit is a 0 or a 1. After that, the SARADC updates the intermediate voltage value to half of the input signal and determines the value of the next highest significant bit based on the result of the comparison. This process is repeated until all bits have been determined.
SARADCs have many advantages, such as low power consumption, small size, and high linearity, so they are commonly used in mobile devices such as cell phones, medical devices, and other applications such as IoT.