The Shepherd's Handbook: Mobile Cyan from Mendocino

Mendocino, a small, artsy, rural county in Northern California, sits quietly on the bluffs of a small bay. It was originally a centuries-old logging village, sparsely populated, the town is mostly Victorian architecture, through the distinctive European colors. The wineries, saunas, gourmet food and hippie village have made it famous in California, not only as an ideal place for literary youths looking for inspiration, but also as a stage for romantic Hollywood movies. The name is also the code name for the first mobile Celeron processor, so we'll start this Shepherd's Handbook in Mendocino.

The introduction of the Celeron brand

IT168 Review Center Before Celeron was introduced, Intel basically used previous-generation products such as the Pentium MMX as a weapon against the Cyrix 6x86, AMD K6, and IDT Winchip, but performance-wise the Pentium MMX was not a The Pentium MMX is not a match for these products in terms of performance, and the Pentium II processor, which is a lower-frequency processor, loses its price advantage against them.

So the Celeron brand was born, and it was clearly positioned at the low end of the market (which at the time meant the sub $1000 PC market). The low price required Celeron to have a low enough cost in both the R&D and production phases, so a simplification based on the mainstream Intel processor at the time yielded a ? New product? was undoubtedly the most cost-effective method. This approach continues to this day, and was largely followed by the AMD Duron series of processors.

The Intel Celeron processor, code-named Covington

The first generation of Celeron processors, code-named Covington, was born in April 1998, and featured 266MHz and 300MHz mainframes and 66MHz FSBs, the same P6 microarchitecture and the same interface (Slot) as the Pentium II processor. architecture and the same interface (Slot1, also known as SEPP242), but the biggest difference is? The biggest difference was that the L2 cache was simplified. The L2 cache was removed as a way to reduce costs and separate product lines. The L2 cache proved to be very important for Intel processors, and without them, Covington had no advantage over its competitors.

The Intel Celeron processor, codenamed Mendocino

Intel quickly recognized the problem and responded quickly, releasing a new Celeron processor, codenamed Mendocino, in August of the same year. Because the Celeron 300A processor (which readers with a little overclocking history will recognize off the top of their heads as the Celeron 300A could almost always be overclocked to 450MHz for stable operation at the time) was clocked at 300MHz as was the previous generation Celeron 300, the model number was distinguished by the addition of the letter "A" at the end of the model number, and the Celeron 333 was released as well. The Mendocino's biggest change from the Covington was the addition of a 128KB L2 cache, which gave it a significant boost in performance, making the Celeron processor a truly cost-effective processor brand.

From 1998 to the present, Celeron processors have undergone several major microarchitectural changes, including the P6 microarchitecture, Netburst microarchitecture, and Core microarchitecture; the core code names have been Covington, Mendocino, Coppermine, Tualatin, and Willamette, Northwood, Prescott, Cedar Mill, Conroe-L and other updates; process technology from the initial 0.25 micron until the current 65nm.

The first mobile Celeron processor

January 25, 1999, Intel released the Mobile Celeron for notebooks. 266 and 300 processors, which were both based on the Mendocino processor core, with 266MHz and 300MHz respectively, a front-side bus frequency of 66MHz, and most importantly, configured with a 128KB L2 cache. Since then, Intel Celeron processors have also entered the mobile computing space.

Intel Mobile Celeron 366 processor with Mendocino core

Intel Mobile Celeron 433 processor with Mendocino core

Like the desktop Celeron, the Mobile Celeron processor is based on the P6 microarchitecture, incorporating The Mobile Celeron processor is based on the P6 microarchitecture, incorporates 32KB of L1 cache and 128KB of full-speed L2 cache, and supports the MMX instruction set. The Mobile Celeron processor is also based on the P6 microarchitecture, incorporating 32KB L1 cache and 12KB full-speed L2 cache, and supports the MMX instruction set. However, there is one important feature that clearly differentiates it from the desktop Celeron: its core voltage is only 1.6V, which is 0.4V lower than that of the desktop Celeron, and it also adds two new power-saving modes: Quick Start and Deep Sleep. The desktop Celeron processors were packaged in SEPP242 and 370-pin PPGA packages, while the Mobile Celeron was packaged in a more compact 615-pin micro-PGA and 615-ball BGA package.

Intel added 1-2 new members to Mobile Celeron every 1-2 months in mid-1999, and by the end of that year the Celeron 266/300/333/366/400/433/466 had formed a fairly large team, with the Celeron 500/533/600 the following year also joined the ranks. Products before the Celeron 466 were definitely on the 0.25 micron process, while those after that may have upgraded to 0.18 micron.

Mendocino Celeron review

Celeron 500 MHzCeleron 466 MHzCeleron 433 MHzCeleron 400 MHzCeleron 366 MHzCeleron 333 MHzCeleron 300 MHzCeleron 266 MHz

Codenames

Mendocino

Main Frequency

500 MHz

466 MHz

433 MHz

400 MHz

366 MHz

333 MHz

300 MHz

Multiplier Frequency

7.5x

6.5x

5.5x

4.5x

Front Side Bus

66 MHz

66 MHz<

66 MHz

L2 cache

128 KB

128 KB.

128 KB

64-bit technology

Not supported

Virtualization technology

Virtualization Technology

Not Supported

EIST

Not Supported

No Support

DBS

No Supported

Not Supported

TXT

Not Supported

EDBit

Not Supported

SIPP

Not Supported

No Support

Not Supported

Production Warranty Years

2+ Yrs

Not Available

7+ Yrs

2+ Yrs

7+ Yrs

2+ Yrs

7+ Yrs

Not Available

Product Status

Released

Released Date

February 14, 2000

< p>September 15, 1999

September 15, 1999

June 14, 1999

May 17, 1999

April 5, 1999

January 25, 1999

Number of cores

Processes

180 nm

250 nm

Core Voltage

2.0V

1.9V

Maximum TDP

27 watts

20.7 watts

19.4 watts

13.8 watts

13.1 watts

11.8 watts

11.1 watts

9.8 watts

Tcase

70 C

70?C

85?C

Package Size

49mm x 49mm

Interface

615-pin micro-PGA, 615-ball BGA

615-pin micro-PGA , 615-ball BGA

615-pin micro-PGA, 615-ball BGA

Remarks 1

All the specifications are for reference only. Please correct me if I am wrong

Remarks 2

EIST, Enhanced Intel SpeedStep TechnologyDBS, Demand Based SwitchingTXT, Trusted eXecution TechnologyEDB, Execute Disable BitSIPP, Stable Image Platform Program