Link to original article How is the 7nm process process realized? - 知乎 (zhihu.com)
嵌牛导读本文介绍了7nm制程工艺如何实现
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嵌牛提问7nm制程工艺如何实现？
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In this article, we explain how the feature sizes in the 7nm process are realized by lithography, and we do not discuss the other 7nm process technologies such as strained silicon and HKMG.
First, let's look at the feature sizes and process parameters of the 7nm process and find the smallest feature size, such as fin width 6nm, fin pitch 27/30nm, gate length 8/10nm, minimum metal pitch 36/40nm, gate pitch 54/57nm. 57nm, the problem we need to consider is how to realize these feature sizes through the lithography process.
Currently, the only two companies that can realize 7nm are TSMC and Samsung, with Samsung using EUV lithography from the beginning, and TSMC starting with DUV and then moving to EUV. In other words, the current 7nm process can be realized using both DUV and EUV, and the following is a description of how DUV and EUV are realized.
Regarding the resolution of the photolithography machine, the highest resolution of the DUV equipment is the ASML 193nm DUV light source, NA 1.35 immersion photolithography machine (immersion), and the equipment model is generally from NXT1950 to NXT2000. For this characteristic wavelength and NA photolithography machine, the resolution can be realized. The limit is 38nm, a single exposure to form a graphic is not less than this limit.
So how do you use a lithography machine with a resolution limit of 38nm to realize a 7nm process?
The two main approaches are double exposure (DE) and self-aligned double patterning (SADP). Double exposure is the use of two separate exposure of different graphics, the superposition of the two exposed graphics to achieve a smaller resolution, of course, if necessary, can also be triple or even more multiple graphics superimposed to achieve a smaller resolution. The disadvantage of double exposure is that it increases the use of lithography, and the overlay error between each lithography pattern has higher requirements, thus increasing the complexity and cost of the process.
In contrast, SADP technology is much simpler, and it is relatively easy to double the size of the lithography pattern, which means that a 20nm pattern can be realized using the DUV lithography machine described above in combination with SADP technology. The DP(193i) in the 7nm process parameter above refers to the use of a 193nm immersion lithography and SADP technology.
We found TSMC's 7nm Design Rules, and we can see that the 7nm process uses a total of 13 metal interconnect layers, M0~M12, of which Fin is the smallest size (6nm), and uses SAQP technology (to be introduced later); and then there is the Poly, or polysilicon Gate process, and a few smaller line widths at the front end of the process. The SADP technology is used in the M0~M4 metal interconnect process.
As shown in the figure below
1) Litho: Firstly, a 40nm photoresist pattern is obtained by a single exposure using photolithography on a wafer that has a hard mask plate (HARD MASK);
2) PR-Slim: Then, the width of the photoresist pattern is reduced by half through an etching process; (This step is not necessary, and depends on the actual process design). (This step is not necessary, depending on the actual process design, the pattern spacing in the example below is 1:1, so PR slim process is needed, so that after the subsequent deposition of SiO2 process, the photoresist around the sidewalls of the space between the adequate spacing; conventional SADP process pattern spacing is generally 1:3, SADP after the formation of the graphic is 1:1, so that there is no need for PR slim)
2: Then through the etching process to make photoresist pattern width by about half; (This step is not necessary, according to the actual process design) )
3) SiO2 depo: and then deposited on the photoresist pattern SiO2 film; (generally use ALD deposition process)
4) Spacer Etch: separately etched off the surface layer of the SiO2 film, so that the SiO2 covered photoresist revealed; and then use another photoresist-only etching process will be in the middle of the photoresist etched, so as to leave the photoresist Finished, which leaves the photoresist graphics on both sides of the sidewalls, become a new template, and realize the PITCH reduced by half; (the use of different chemical compositions of the plasma etching can be realized in different materials of selective etching)
5) HM Etch: using the sidewalls left behind as a mask, and then downward etching, you can transfer the graphics on the Hard mask;
6) Clean: Finally, clean off the surface layer of SiO2/ARC, etc., and then get the characteristic size of 20nm pattern, the pattern spacing is 1:1, to achieve the results of the resolution is reduced by half;,
Therefore, in the use of DUV lithography to realize the 20nm pattern, SADP is a simple and effective method. However, SADP also has its own problems, for example, resolution reduction is achieved by duplicating a line into two identical smaller lines, i.e., the two newly generated lines are identical in shape, so this method is only suitable for relatively simple patterns with a lot of repetitive structures.
At the same time, the newly generated graphic is a closed loop (as shown in patterning step2 below), so the SADP-generated graphic also requires a cutting process to remove unwanted parts of the graphic; as shown in the figure below, so in order to realize the final graphic we need, the graphic is actually designed to be split into two parts, and it is the final combination of these two parts that is the final graphic we need. The final combination of the two parts of the graphic is the graphic we need, so the SADP process of graphic splitting is also a complex process.
Then there is SAQP ? (self-aligned quadruple patterning) to realize the Fin structure with the smallest line width in the 7nm process. SAQP is very similar to SADP, in that it is equivalent to using SADP again after using SADP once, which results in a quadruple reduction in line width, i.e., a 10nm pattern.
Below is a flowchart of a Fin structure fabricated using SAQP, where the 4 patterns initially created by lithography have been transformed into 16 patterns after the SAQP process, and reduced in size to 1/4 of the original size. Fin, as the base unit of a Finfet integrated circuit, is highly reproducible and simple, and therefore very well suited for the use of SAQP.
Fin, as the base cell of Finfet integrated circuits, is highly reproducible and therefore ideal for SAQP technology.
At the same time, the high aspect ratio of the Fin structure itself creates a wedge shape in the Fin etch process as shown in the figure below, which results in a Fin tip that is smaller than the final mask size created by the SAQP process, resulting in a Fin structure with a line width of 6nm in the final product.
An electron microscope image of the Fin in a 7nm Finfet, with a tip width of approximately 6nm.
This concludes the realization of the critical dimensions of the 7nm process using DUV lithography with SADP/SAQP, followed by the EUV process.
EUV lithography benefits from the use of 13.5nm EUV as the light source, and the resolution limit of a single exposure can reach 13nm, so feature sizes in the 7nm process can basically be accomplished with a single exposure. EUV can also use SADP technology to achieve even smaller feature sizes, allowing the chip process to continue to evolve to 5nm/3nm. The EUV can also utilize SADP technology to achieve smaller feature sizes, allowing the chip process to continue to evolve to 5nm/3nm.
Below is a diagram showing the DUV and EUV approaches to achieving smaller feature sizes:
While both DUV and EUV are capable of achieving 7nm, EUV has a technological advantage over DUV in terms of better image quality and fewer process steps, which is very favorable in terms of both cost and final yield.
The graph below compares the number of lithography process steps and registration error steps for different process nodes. From 28nm to 7nm, the number of lithography process steps using Immersion DUV equipment increases to 34, and the number of registration error steps reaches more than 60, which is a huge challenge for process integration with such high process complexity, but also greatly improves the final product yield. This high process complexity is a huge challenge for process integration and greatly increases the risk of yield loss in the final product. As a result, the continued use of Immersion DUV equipment for sub-7nm process development has become nearly impossible, and is starting to become uneconomical.
The introduction of EUV has greatly reduced the complexity of the process, and the number of lithography steps required for 7nm EUV is about the same as that for 20nm DUV, so the introduction of EUV has made it possible to continue to develop sub-7nm processes, and Moore's Law continues to be alive and well.
The ASML EUV roadmap below shows that as the NA of the EUV device increases, the final resolution of the EUV can be less than 7nm, making 2nm possible.
At this point, the lithography implementation of the 7nm process through DUV and EUV has been fully described.
While smaller feature sizes can be achieved with better lithography, it is not as easy as just getting good equipment, and there are a number of complex resolution enhancements that need to be made in order to realize the resolution limits of the equipment. At the same time, as the device feature size is reduced, individual devices need to be redesigned to address the short channel effect (SCE), hot carrier injection (HCI), and gate oxide leakage associated with the reduced device size.