By Heart of the Machine
Edited by Dimension and Ping Chen
As the most fundamental building block of a computer chip, transistors are getting smaller and smaller, which makes them faster and more energy efficient. Currently, 7nm and 5nm processes are the dominant choices for chips used in cell phones and laptops, and in March 2021, Samsung announced the world's first 3nm 'SRAM chip', which is expected to be in mass production from 2022 onwards.
IBM was the first to show off the world's first 2nm chip manufacturing technology in a stimulating competition between major chip makers.
On the evening of May 6, IBM announced an important breakthrough in semiconductor design and process: the world's first chip with a 2nm process, which will help elevate the semiconductor industry to a new level. Compared with the current mainstream 7nm chip, IBM 2nm chip performance is expected to improve 45%, 75% lower energy consumption. The 2nm chips are also smaller and faster than the current leading 5nm chips.
Specifically, the potential advantages of 2nm chips include the following:
In more specific detail, the IBM 2nm chip holds 333 million transistors per square millimeter, compared to TSMC's 5nm chip, which holds 171.3 million transistors per square millimeter, and Samsung's 5nm chip, which holds 127 million transistors per square millimeter.
As a former major chip maker, IBM now outsources its chip production to Samsung, but still maintains a chip manufacturing research and development center in Albany, New York. The center is responsible for test runs of chips and has signed joint technology development agreements with Samsung and Intel to use IBM's chip manufacturing technology. The 2nm chips announced here were designed and manufactured here.
Higher transistor density, new architectural design
Compared to 7nm processors, IBM's 2nm chips offer a 45% increase in performance at the same power, and are 75% more energy efficient. IBM noted that they were the first to introduce 7nm, 5nm research in 2015 and 2017 respectively. IBM noted that they were the first research organization to introduce 7nm in 2015 and 5nm in 2017, the latter of which has been upgraded from FinFET to nanosheet technology, which allows for better customization of the voltage characteristics of individual transistors.
IBM says the technology can fit 50 billion transistors onto a chip the size of a fingernail, giving processor designers more options, such as the ability to inject core-level innovation to improve the functionality of cutting-edge workloads such as AI and the cloud, as well as explore new ways for hardware to enforce security and encryption.
As you know from time to time from other reports, different chip foundries (TSMC, Samsung, etc.) have different definitions of transistor density. It's worth noting that these numbers on density are usually listed as peak density.
Regarding the Gate-All-Around / nanosheet, a key technology for how transistors are made in the new process, while IBM hasn't made it clear, the images show that this new 2nm processor uses a three-stack GAA design.
In the current new process race, Samsung plans to introduce GAA (Samsung calls its technology MBCFET) at the 3nm node. It plans to start risky trial production of MBCFETs by the end of 2020, with volume production at scale in 2021, and an optimized version of its first-generation MBCFET in 2021. TSMC, on the other hand, still wants to continue to use FinFETs at 3nm, and will wait until 2nm chips to launch GAA. according to the plan, TSMC's 2nm process will start risk trial production in 2023 and mass production in 2024.
In contrast, Intel can be expected to introduce some form of GAA on its 5nm process, and the company is expected to move away from FinFETs at the 5nm node and toward GAA surround-gate transistors by 2023.
Just as the FinFET process saved the chip industry with its current mass adoption, GAAFET may be the key to keeping the semiconductor industry moving forward in the sub-5nm era. However, the manufacturing difficulty of the GAAFET process is obviously extremely high.
IBM's 3-stack GAA design uses a cell height of 75nm, a cell width of 40nm, and individual nanosheets that are 5nm high and 5nm apart from each other, with a gate pitch of 44nm and a gate length of 12nm. 3-stack GAA is the first design to utilize a bottom dielectric isolation channel, which makes a 12nm gate length possible, and its gate length is 12nm, according to IBM. gate length possible, and its internal spacer is designed using a second-generation dry process that facilitates nanosheet development, IBM said.
During implementation, IBM also made extensive use of EUV technology and included EUV patterning at the front end of the chip process, not just at the middle and back end, which is now widely used in the 7nm process. Importantly, all of the key features on this chip will be etched using EUV lithography, and IBM has also figured out how to use single-exposure EUV to reduce the number of optical masks used to etch the chip.
No details have been provided on the 2nm test chip, which at this stage is likely to be a simplified SRAM test tool with little logic, and IBM has indicated that the test design uses a multi-Vt scheme for high-performance and high-efficiency application demonstrations.
While the 2nm process chips are more powerful than the current 7nm and 5nm in terms of both performance and energy consumption, they are largely proof of concept and a long way from market. In July 2015, the same IBM was the first to announce that it had made a 7nm chip, and it won't be until the second half of 2019 that people will be able to buy phones with 7nm chips.
It's been reported that it will take a couple of years for 2nm technology to reach the market.
Reference links:
/show/16656/ibm-creates-first-2nm-chip
/technology/ibm-unveils-2-nanometer-chip-technology-faster- computing-2021-05-06/
/2021/5/6/22422815/ibm-2nm-chip-processors-semiconductors-power-performance-technology
/2021-05- 06-IBM-Unveils-Worlds-First-2-Nanometer-Chip-Technology,-Opening-a-New-Frontier-for-Semiconductors#assets_all