Ad 1672 is a new single-chip analog-to-digital converter (adc) recently introduced by ADI. The chip has four high-performance sample-and-hold amplifiers (sha), four flicker ADCs and a voltage reference. It adopts four-stage pipeline structure with output of error correction logic circuit and bicmos process, which ensures the accuracy of 12 bits at 3msps sampling speed and does not lose codes in the whole working temperature range. Because the input sha of ad 1672 has the characteristics of fast settling, it is suitable for multi-channel systems with voltage switching from negative full scale to positive full scale, and also for single-channel sampling with input frequency as high as Nyquist rate. Ad 1672 has the characteristics of broadband input, single power supply, low power consumption and low price, which is very suitable for new circuit design of communication, image processing and medical equipment.
Ad7892br- 1 ┃ 12-bit serial ADC.
4 AD7893 LC2 MOS 12-bit serial 6 us ADC with built-in fast l2 ADC, and the conversion time is 6US; 8-lead SOIC package; Single power supply operation; High speed, easy to use, serial interface; On-chip sample-and-hold amplifier: low power consumption: 25mW
5 AD9637 is an 8-channel, 12-bit, 40 MSPS/80 MSPS analog-to-digital converter (ADC) with on-chip sample-and-hold circuit, which is specially designed for low cost, low power consumption, small size and ease of use. The conversion rate of this product can reach up to 80 MSPS, with excellent dynamic performance and low power consumption, which is very meaningful for small package size applications. ADC needs a single power supply of 1.8 V and a sampling rate clock signal compatible with LVPECL/CMOS/LVDS to give full play to its working performance. For most applications, no external reference or driver is required.
In order to obtain the appropriate LVDS serial data rate, ADC will automatically double the sampling rate clock. It provides a data clock output (DCO) for capturing data at the output and a frame clock output (FCO) for sending new output byte signals. It also supports each channel to enter the power-saving state independently; When all channels are disabled, the typical power consumption is less than 2mW.