CMOS: Complementary Metal Oxide Semiconductor, Complementary Metal Oxide Semiconductor
CISC (Complex Instruction Set Complex Instruction Set Computer (CISC)
COB (Cache on board)
COD (Cache on Die)
CPGA (Ceramic Pin Grid Array)
CPU: Center Processing Unit (CPU)
EC (Embedded Controller)
FEMMS: Fast Entry/Exit Multimedia State
FIFO: First Input First Output, First In First Out Queue
FPU: Float Point Unit
HL-PBGA: Surface Adhesive, Highly Heat Resistant, Thin and Lightweight Plastic Ball Matrix Package
IA: Intel Architecture. Intel Architecture
ID: identify, identification number
IMM: Intel Mobile Module, Intel Mobile Module
KNI (Katmai New Instructions, Katmai New Instruction Set, i.e. MMX2)
MMX: MultiMedia Extensions
NI: Non-Intel
PGA: Pin-Grid Array, power hungry
PSN (Processor Serial Number)
KNI: Katmai New Instructions, or MMX2
KNI: Katmai New Instructions, or MMX2
MMX. numbers, Processor Serial Number)
PIB: Processor In a Box(Processor in a Box)
PPGA(Plastic Pin Grid Array)
PQFP(Plastic Quad Flat Package)
PQFP(Plastic Quad Flat Package)
RISC (Reduced Instruction Set Computing)
SEC: Single Edge Connector
SIMD: Single Instruction Multiple Data Multiple Data Streaming
SiO2F (Fluorided Silicon Oxide)
SOI: Silicon-on-insulator
SSE (Streaming SIMD Extensions)
TCP: Single Edge Connector, Single Edge Connector
SEC: Single Edge Connector, Single Edge Connector
SEC: Single Edge Connector, Single Edge Connector
SIMD: Single Instruction Multiple Data p>
TCP: Tape Carrier Package (TCP), low heat
TLBs (Translate Look side Buffers)
VLIW (Very Long Instruction Word)
WHQL: Microsoft Windows Hardware Quality Lab
AGP: Accelarated Graphic Port, a bus structure for the CPU and graphics chip
APIC. Advanced Programmable Interrupt Controller
BGA: Ball Grid Array
BTB/C: Branch Target Buffer/Cache
CC: Companion Graphic Port, a CPU and graphics chip bus structure.
CC: Companion Chip, the motherboard chipset of the MediaGX system
CISC: Complex Instruction Set Computing
CMOS: Complementary Metal Oxide Semiconductor (Complementary Metal Oxide Semiconductor)
CP: Ceramic Package
CPGA: Ceramic Pin Grid Array
CPU: Centerl Processing Unit (
DCT: Display Compression Technology
DIB: Dual Independent Bus, including L2cache bus and PTMM (Processor To Main Memory). CPU To Main Memory) bus
DP: Dual Processing
DX: A CPU that includes a math coprocessor ECC: Error Check Correct
ECRS: Entry Call Return Stack
ECRS: Entry Call Return Stack
DX: A CPU that includes a math coprocessor.
ECRS: Entry Call Return Stack, which stores the return address instead of RAM.
EPIC: Explicitly Parallel Instruction Computing, a 64-bit instruction set
FPU: Floating-point Processing Unit
FRC. Functional Redundancy Checking, a feature only available on dual-processors
IA: Intel Architecture
I/O: Input/Output
It's all about the power. Output)
IS: Internal Stack
ISO/MPEG: International Standard Organization's Moving Picture Expert Group
L1cache: Level 1 cache, usually integrated into the CPU, but now there are also designs that integrate L2cache into the CPU, such as entium2 LB: Linear Burst, a special technology used in the Cyrix 6x86.
MADD: Multiply-Add instruction
MAG: Multiply-Accumulate instruction, multiply two floating-point numbers and then add them to another floating-point number, which can dramatically increase the speed of 3D graphics
MHz: Mega Hertz unit of operating frequency, 1GHz=1000MHz
MIPS. Million Instructions per Second (每秒钟百万条指令), is a parameter of CPU speed, of course, the bigger the better
MMX: Multimedia Extensions (this should be very familiar to you, this CPU has 57 new 64-bit instructions, is the biggest change since the 386, there are also SIMD architecture and so on.
MPGA: Micro PGA, smaller than TCP in terms of heat dissipation and size
PGA: Pin Grid Array, high power consumption, suitable for desktops
pin: CPU pin PLL: Phase Lock Loop
PR: P-rating, is a rated performance index to Winstone 96 test as a basic (PR2 with Winstone97), such as PR-75 that is equivalent to the Pentium 75 RISC: Reduced Instruction Set Computing (Reduced Instruction Set Computing), is relative to the CISC is concerned ROB: Reorder Buffer (Reorder Buffer), is the most important of all. ROB: Reorder BufferSC: Static Core
SEC: Single Edge Contact, Intel's Pentium2 CPU case
Slot 1: Pentium2 motherboard.
Slot 1: Pentium2 motherboard, external bus frequency 66MHz
Slot 2: Intel's next-generation chipset socket, the local bus frequency of more than 100MHz, with a larger SEC, the main purpose of the server, at the same time, can be installed 4 CPU SMM: System Management Mode, is a kind of energy-saving mode
Socket 7: Socket for Pentium-class (classic Pentium and P55C) CPUs, with an external bus frequency of 83.3MHzSocket 8: Socket for high-performance Pentium-class CPUs, with an external bus frequency of 66MHz
Socket 8: Socket for high-performance Pentium-class CPUs, with an external bus frequency of 66MHz
Specialized Data Rate (SDR): The maximum possible speed for the data transfer rate of the CPUs in the SATA Revision 2.0 (SATA Revision 2.0). SRR: Segment Register Rewrite
SRAM: Static Random Access Momory SUPER-7: Increased Socket 7, External Bus Frequency 100MHz, AGP, L2/L3cache, PC98. 100MHz SDRAM
SX: CPU without Math Co-Processor
TCP: Tape Carrier Package, low heat, suitable for notebook PCs.
TLB: Translation Look side Buffer VMA: Unified Memory Architecture, for system memory and display memory Vcc2: Provides voltage to the CPU's internal core Vcc3 (CLK) Provides voltage to the CPU's input and output signals VLIW: Very Large Input and Output Signals VLIW: Very Long Instruction Word (极长指令字) VRE: Voltage Reduction Enhancement (增强形电压调节) VSA: Virtual System Architecture (虚拟系统架构) Write-Back (写回): yes Write-Though: is a way of working with L1cache
CPU
3DNow! Address Generation Units)
BGA (Ball Grid Array)
BHT (Branch Prediction Table)
BPU (Branch Processing Unit)
Brach Pediction
CMOS: Complementary Metal Oxide Semiconductor
CISC (Complex Instruction Set Computing)
CLK (Clock Cycle)
COB (Cache on board)
COD (Cache on Die)
CPGA (Ceramic Pin Grid Array, Ceramic Pin Grid Array, Ceramic Pin Grid Array, Ceramic Pin Grid Array, Ceramic Pin Grid Array, Ceramic Pin Grid Array, Ceramic Pin Grid Array) CPGA (Ceramic Pin Grid Array)
CPU (Center Processing Unit)
Data Forwarding
Decode
DIB (Dual Independent Bus)
EC (Embedded Controller)
Embedded Chips
EPIC (explicitly parallel instruction code)
EPIC (parallel Instruction Code)
FADD (Floationg Point Addition)
FCPGA (Flip Chip Pin Grid Array)
FDIV (Floationg Point Divide)
FEMMS: Fast Entry/Exit Multimedia State
FFT (fast Fourier transform)
FID (FID: Frequency identify, Frequency Identification Number )
FIFO (First Input First Output)
flip-chip
FLOP (Floating Point Operations Per Second)
FMUL ( Floating Point Multiplication)
FPU (Float Point Unit)
FSUB (Floating Point Subtraction)
GVPP (Generic GVPP (Generic Visual Perception Processor)
HL-PBGA: Surface Adhesive, Highly Heat Resistant, Thin and Lightweight Plastic Spherical Matrix Package
IA (Intel Architecture)
ICU (Instruction Control Unit)
ID: identify, identification number
IDF (Intel Developer Forum)
IEU (Integer Execution Units)
Instructions Cache
Instruction Coloring
IPC (Instructions Per Clock Cycle)
IPC (Instructions Per Clock Cycle)
ISA (instruction set architecture)
KNI (Katmai New Instructions)
Latency
LDT (Lightning Data Transport, Lightning Data Transmission)
LDT ( Lightning Data Transport, Lightning Data Transport bus)
Local Interconnect
MESI (Modified, Exclusive, Shared, Invalid: Modified, Excluded, ****ed, Deprecated)
MMX (MultiMedia Extensions, Multimedia Extensions Instruction Set)
MMU (Multimedia Unit)
MFLOPS (Million Floationg Point/Second)
MHz ( Million Hertz)
MP (Multi-Processing)
MPS (MultiProcessor Specification)
MSRs (Model-Specific Registers)
NAOC (no-account OverClock)
NI: Non-Intel
OLGA (Organic Land Grid Array
OoO (Out of Order)
PGA: Pin-Grid Array,Power Consumption
Post-RISC
PR (Performance Rate)
PSN ( Processor Serial numbers)
PIB(Processor In a Box)
PPGA(Plastic Pin Grid Array)
PQFP(Plastic Quad Flat Package)
RAW (Read after Write)
Register Contention
Register Pressure
Register Renaming
Remark
Resource contention
Retirement
RISC (Reduced Instruction Set Computing, Reduced Instruction Set Computing, Reduced Instruction Set Computing, Reduced Instruction Set Computing, Reduced Instruction Set Computing, Reduced Instruction Set Computing, Reduced Instruction Set Computing, Reduced Instruction Set Computing) Computing)
SEC: Single Edge Connector
Shallow-trench isolation
SIMD (Single Instruction Multiple Data, Single Instruction Multiple Data Stream)
SiO2F (Fluorided Silicon Oxide)
SMI (System Management Interrupt)
SMM (System Management Mode. SMM (System Management Mode)
SMP (Symmetric Multi-Processing)
SOI: Silicon-on-insulator
SONC (System on a chip)
SPEC (System on a chip, System on Integrated Chip)
SPEC (System Performance Evaluation Corporation, System Performance Evaluation Test)
SQRT (Square Root Calculations)
SSE (Streaming SIMD Extensions. SSE (Streaming SIMD Extensions)
Superscalar
TCP: Tape Carrier Package, low heat generation
Throughput
TLB (Translate Look side Buffers)
USWC (Uncacheabled Speculative Write Combination)
VALU (Vector Arithmetic Logic Unit)
VLIW (VLIW) is the most powerful and efficient way of writing data.
VLIW (Very Long Instruction Word)
VPU (Vector Permutate Unit)
VPU (vector processing units, i.e., where MMX, SSE, etc. are processed)
VPU (vector processing units, i.e., where MMX, SSE, etc. are processed)
VALU (Vector Arithmetic Logic Unit)