The SPI bus system is a synchronous serial peripheral interface that enables the MCU to communicate with a variety of peripheral devices in serial mode to exchange information. Peripheral settings FLASHRAM, network controllers, LCD display drivers, A/D converters and MCUs, etc. The SPI bus system can be directly interfaced with a wide range of standard peripheral devices produced by various manufacturers, and the interface generally uses four lines: the serial clock line (SCK), the host input/slave output data line MISO, the host output/slave input data line MOSI, and the low-level valid slave select line SS (some SPI interface chips come with an interrupt signal line INT or INT, some SPI interface chips do not have a host output/slave input data line MOSI).The communication principle of SPI is very simple, it works in a master-slave mode, which usually has one master device and one or more slave devices, and requires at least 4 wires, and in fact 3 can be fine (for unidirectional transmission) The Also all SPI based devices **** have them, they are SDI (data in), SDO (data out), SCK (clock), CS (chip select).
(1) SDO - Master device data output, Slave device data input
(2) SDI - Master device data input, Slave device data output
(3) SCLK - Clock signal, generated by master device
(4) CS - Slave enable signal, controlled by the master device where CS controls whether the chip is selected or not, i.e. the operation of this chip is valid only if the chip select signal is a predefined enable signal (high or low). This allows multiple SPI devices to be connected on the same bus.
The next three wires are responsible for communication. Communication is accomplished by exchanging data, and it is important to realize that SPI is a serial communication protocol, which means that the data is transferred one bit at a time. This is the reason why the SCK clock line exists, the clock pulse is provided by SCK, SDI, SDO is based on this pulse to complete the data transfer. The data output is via the SDO line and the data is changed on the rising or falling edge of the clock and read on the immediately following falling or rising edge. To complete the one bit data transfer, the same principle is used for the inputs. In this way, at least eight changes of the clock signal (one on the rising and one on the falling edge), an eight-bit data transfer can be accomplished.
It is important to note that the SCK signal line is controlled only by the master device; the slave devices cannot control the signal line. Again, in an SPI-based device, there is at least one master device. Characteristics of such a transmission: Such a transmission has the advantage that, unlike ordinary serial communication, which continuously transmits at least 8 bits of data at a time, SPI allows the data to be transmitted one bit at a time, and even allows pauses because the SCK clock line is controlled by the master device, and the slave device does not collect or transmit data when there is no clock jump. That is to say, the master device can complete the control of the communication through the control of the SCK clock line.SPI is also a data exchange protocol: because the data input and output lines of SPI are independent, it allows data input and output to be accomplished at the same time. The implementation of different SPI devices is not the same, mainly data change and acquisition of different time, in the clock signal on the upper edge or lower edge of the acquisition of different definitions, please refer to the relevant device documentation.
In point-to-point communication, the SPI interface does not require addressing operations, and is full-duplex communication, which is simple and efficient. In a system with multiple slave devices, each slave device requires a separate enable signal, and the hardware is slightly more complex than an I2C system.