When JK flip-flop has clock pulse effect, when J and K are both 0, the state remains unchanged. When j is 0 and k is 1, the secondary state is 0; When j is 1 and k is 0, the secondary state is1; When J= 1 K= 1, the secondary state is opposite to the current state. D flip-flop (composed of NAND gate), whose logical function is that when D= 1, Q = 0；; When D=0, q =1;
Second, the difference between the trigger mode:
JK flip-flops trigger on the clock edge, usually the rising edge RS. D flip-flops are divided into high-level trigger and low-level trigger, and there are also three trigger modes of clock edge trigger.
Extended data flip-flop is a binary memory device with memory function and one of the basic devices of various sequential logic circuits. Its structure includes three circuits: synchronous circuit, master-slave circuit and blocking and holding circuit. Flip-flops can be divided into RS flip-flops, JK flip-flops, D flip-flops and T flip-flops. According to the trigger mode of the circuit, it can be divided into master-slave trigger and edge trigger.
At present, TTL integrated flip-flops produced in China mainly include edge D flip-flop, edge JK flip-flop and master-slave JK flip-flop. These triggers can be converted into triggers with other functions, but the trigger mode of the converted triggers remains unchanged. For example, a trigger from an edge transition is still edge triggered.
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Baidu encyclopedia -JK trigger
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