When it comes to the bus, the pulse may not be very clear, including many old birds. Let's take a look below!
The CPU needs to exchange data with a variety of peripheral hardware devices, and if each device is introduced into a group of lines directly connected to the CPU, it will lead to a disorganized system line. In order to simplify the hardware circuit and system structure, the computer introduced a set of multiple devices *** with the use of data transmission lines (bus), the CPU through the bus and a variety of peripheral hardware devices connected to the bus, and through the bus for data exchange. In other words, the bus is a public **** pathway for transmitting data between various components in the computer.
A bus performance parameters
The main performance parameters of the bus are bus bandwidth, bus bit width and bus operating clock frequency.
1. Bus bandwidth
Bus bandwidth, also known as the bus transmission rate, is used to describe the bus to transmit data faster or slower. It is the amount of data that can be transmitted per unit of time (per second) on the bus, and is commonly used in units of MB/s. For example, the AGP bus bandwidth that complies with the AGP 2× specification is 528MB/s.
2. Bus Bit Width
Bus bit width refers to the amount of data that the bus can transmit at a time in binary digits, and is measured in bits (位)。 We often refer to 32 bit (bit), 64 bit (bit) that is the bus width. The larger the bus bit width, the more data is transmitted through the bus each time, and the larger the bus bandwidth.
3. Bus operating clock frequency
Bus operating clock frequency is referred to as the bus clock to describe the speed of the bus, with the number of times per unit of time (per second) can be transmitted data on the bus, the bus clock is commonly used for MHz. the higher the frequency of the bus clock, the more the number of times per unit of time to transmit data over the bus, the greater the bandwidth of the bus.
Because different devices in the computer at different speeds, the amount of data needed is different, and thus the bus clock to different devices is not the same, the need for the system clock (generated by a crystal mounted on the motherboard, a fairly accurate and stable pulse signal generator) by the frequency division of the supply to the different devices and the bus use.
For example, for a system consisting of a PIII CPU motherboard installed with a 133 MHz external frequency, the system clock is 133 MHz, the CPU external and internal buses operate at 133 MHz; the AGP channel operates at 66 MHz (133 × 1/2 MHz, dichroic); and the PCI bus operates at 33 MHz (133 × 1/4 MHz, dichroic). frequency), the operating clocks of AGP and PCI are generated by the frequency division circuit. (From the frequency division we can see why sometimes we overclock to 75MHz and 83MHz called non-standard external frequency? Because such an external frequency can not be averaged after the frequency division, resulting in the computer can not work stably.)
4. Bandwidth, bit width, bus clock relationship
Bus bandwidth = bus bit width × bus clock
For example: PCI bus bit width of 32 bits, the bus clock frequency of 33MHz; then the PCI bus bandwidth = 32 bit × 33MHz / 8 = 132 MB / s (in addition to the 8 is the bit converted to Byte, 1 Byte =8 bit).
Second, the bus function
By the function of the bus (the content of the transfer of information) classification, there are three types of computers in the bus, that is, the data bus to transmit data information, the address bus to transmit address information and control bus to transmit a variety of control information.
1. Data bus
The data bus is a bus that transmits data information (various command data information) between the CPU and memory, and between the CPU and I/O interface devices. These signals are sent to and from the CPU and memory, and between the CPU and I/O interface devices via the data bus, and therefore, the information on the data bus is transmitted in both directions.
2. Address bus
The address bus transmits address information from the CPU to the memory and the I/O interface devices. Addressing capability is a unique function of the CPU, and the address information transmitted on the address bus is only issued by the CPU, so the information on the address bus is transmitted in one direction.
3. Control bus
The control bus transmits a variety of control signals, including control signals from the CPU to the memory and I/O interface devices, and answer signals and request signals from the I/O interfaces to the CPU; therefore, the information on the control bus is transmitted in both directions. Control signals include timing signals, status signals and command signals (such as read and write signals, busy signals, interrupt signals) and so on.
For example, writing data to memory is carried out through a memory bus (including a data bus, an address bus, and a control bus), and data information needs to be transmitted to the memory through the data bus, and which cells of the memory must be written to the address bus to transmit the address information to determine, and which moment to start writing data to the memory is determined by the control signals obtained from the control bus.
^14030301a^1 is a 64-word 1-bit static memory C850 logic block diagram, to write (or read) data to a cell of the memory, a need to transmit address information to the address bus consisting of A0, A1, A2, A3, A4, A5, in order to determine which memory cell to write (or read); the second is the need to transmit a chip select control signal to the CE terminal To make the memory chip in the operating state; Third, the need to transmit read and write control signals in the R / W end to determine the write (or read out) operation; so that from the data input terminal Din (or data output terminal Dout) to write (or read out) data. The above operations transmit information to the address line, the control line, and the data line.
Some special buses, although they also need to transmit data information, address information and control signals, do not provide separate data buses, address buses and control buses due to their simple structure. Such as universal serial bus USB, including power lines, ground lines, including the total *** only provides four lines, can only be transmitted in a serial mode of delivery time-sharing data information, address information and control information.
Three, external frequency, main frequency and front-end bus
CPU internal oscillator, but relies on the external crystal oscillator circuit to obtain the clock signal, so that the regular execution of instructions, this external crystal oscillator to provide the clock frequency of the CPU is called the external frequency. This external clock frequency is called the external frequency. Both the internal and external data transmission buses of the CPU are based on this basic operating frequency.
While the CPU does not have its own clock signal generator, it does have an internal clock multiplier circuit, which is used to boost the actual operating frequency of the CPU. The clock multiplier circuitry increases the system clock signal (i.e., the external CPU frequency, e.g., 133MHz) sent from outside the CPU by a certain ratio factor (i.e., multiplier), to obtain the frequency at which the CPU actually operates (i.e., the main frequency, which is also the bus frequency inside the CPU, Note 1). Therefore, CPU main frequency = CPU external frequency × multiplier frequency. For example, if the external frequency of PⅢ733 is 133MHz, and the multiplier frequency is 5.5, the actual operating frequency of CPU is 733MHz (133MHz×5.5).
Note 1: The CPU internal bus refers to the bus used to transfer data between the arithmetic logic component ALU, controller, decoder, memory management component, instruction prefetching component, and bus components inside the CPU chip.
Another, more confusing concept is the front side bus, which is the channel that transfers data between the motherboard chipset (Northbridge chip) and the CPU, and thus is also known as the external CPU bus, ^14030301b^2 for the internal CPU bus process. Before the release of Athlon, there was no difference between the operating frequency of the front side bus and the external frequency, they were all the same frequency. For example, the PIII733 has an external frequency of 133MHz, and its front side bus also works at 133MHz. In such a case, the data transmission bandwidth provided by the front-end bus of PⅢ is only 1064 MB/s (64bit×133MHz/8), which can't meet the data transmission requirements of high main frequency CPUs (the theoretical bandwidth of data transmission of the CPU internal bus is 32bit×733MHz/8=2932MB/s), so the CPU manufacturers improved the front-end bus technology to increase the data transfer bandwidth of the front side bus.
After the release of AMD's Athlon with Alpha EV6 technology, the data transfer bandwidth of its front-side bus was twice that of processors without EV6 technology at the same operating frequency, and the Athlon's front-side-bus-equivalent operating frequency no longer equaled the CPU's external frequency, but was instead twice as much as it was.The main technical feature of EV6 is that it utilizes the double-pulse-along data transfer technology (Note 2), which increases the data transmission bandwidth of the front-end bus to twice its original value of 1.6GB/s (64bit×2×100MHz/8=1.6GB/s) at a clock frequency of 100MHz, so that the equivalent front-end bus operating frequencies are 200MHz (1.6GB/s÷64bit=1.6GB/s÷8B= 200MHz), and 266MHz (2.1 GB/s ÷ 64bit = 266MHz). Intel's P4 processor working at an external frequency of 100MHz, due to the use of four 64-bit wide front side bus (i.e., we often refer to the four-channel front side bus, each channel of the front side bus is still 100MHz, but the four channels add up to the equivalent of 400MHz), so that the front side bus data transfer bandwidth to the original quadruple to reach the 3.2 GB/s (64bit x 4bit x 8B = 200MHz). (64bit×4×100MHz/8=3.2GB/s), so its equivalent front bus operating frequency is 400MHz (3.2GB/s÷64bit=400MHz).
So now we often talk about the front-side bus (FSB: Front System Bus) frequency actually refers to the front-side bus equivalent operating frequency, that is, FSB = front-side bus equivalent operating frequency = front-side bus bandwidth ÷ front-side bus bit width, so that the frequency of the front-side bus and the original external operating frequency (i.e., the external frequency of the CPU) to distinguish between The bit width of the front bus in the formula is the bit width of the CPU's external data bus, and the current mainstream CPU's data bus bit width is 64 bits.
Note 2: Dual-pulse along the data transfer technology is to improve the bus bandwidth of a technology, the traditional bus data transfer, only in the bus clock pulse signal falling edge (or rising edge), and dual-edge data transfer technology in the pulse signal up and down the edge of the data transfer in the case of not increasing the bus bit-width and bus clock frequency, the bus bandwidth increased by a factor of two. At present, many buses in the PC use the dual-edge data transfer technology. For example, the DDR memory and EV6 buses apply this principle.
In fact, the CPU external frequency and front-end bus describes the data transmission between the CPU and the outside, only the angle of description is not the same. the CPU external frequency is purely from the CPU's external clock generator, while the front-end bus is from the angle of the data transmission speed. the CPU is relying on multiplier circuits to achieve higher actual operating frequency, the same as the CPU multiplier circuits, the front-end bus is relying on advanced technology to achieve the actual operating frequency, and the front-end bus is relying on advanced technology to achieve the actual operating frequency. The front-end bus relies on advanced technology (EV6 and quad-channel front-end bus designs) to achieve double or quadruple the actual operating frequency, ^14030301c^3 shows a schematic diagram of the data transfer along.
An analogy, 1 working year is divided into 365 days (if you consider 1 year as 1 second, the frequency of the working year is 365Hz, and the period is 1/365 years, i.e., 1 day as a cycle), which is the arrangement of nature, fair and unchangeable for anyone, and belongs to the external force, which is equivalent to the external frequency of the CPU. And every day (i.e., within a cycle) everyone accomplishes different things (equivalent to the instructions executed by the CPU). Ordinary people complete one thing a day, while people with better working ability can divide the day into two half days, each half day to complete one thing, then he can complete two things in a day (equivalent to Duron, Athlon processor), and smart people, he will add three helpers, then a day can complete four things (equivalent to P4 processor). The situation we see is this, the time does not change, the same are the time of day, that is, the external frequency is fixed, and in the same time to complete the workload is not the same (equivalent to the amount of data transferred per unit of time is not the same), and therefore the actual efficiency of the work (equivalent to the equivalent operating frequency of the front-end bus is the same) is not the same.
In the history of PC development, CPUs and peripherals at different times required different amounts of data, and thus the bus architecture of motherboards at different times was different. Since the 386DX, the data bus bit-width of the CPU has increased to 32 or even 64 bits, and the motherboard bus architecture is constantly changing.
Four, motherboard bus architecture
Multiple devices use the same bus to exchange data, and the signals between them can interfere. Therefore, the actual design of the motherboard bus, will be in the CPU, system memory, I / O expansion slots and peripheral interfaces between the chip to add buffers (its role is to isolate the transmitted signal, shaping, delay), these buffers will be a single bus into a different level of the bus ^ 14030301d ^ 4.
1. CPU bus will be the CPU (through the address buffer and the data buffers) to peripheral chips for data access to memory, I/O channels, and peripheral interfaces.
2. The system memory bus is used to connect the memory controller and memory (via buffers) to realize data access to memory.
3. The I/O channel bus (also known as the expansion bus) connects various expansion boards on the I/O expansion slots, and the CPU and system memory exchange data with various expansion boards through the I/O channel bus. In order to make the boards produced by various manufacturers have compatibility, I/O channel bus must have a unified standard, different I/O channel bus data bus, address bus bit width, different operating frequency.
4. Peripheral interface bus is connected to the motherboard peripheral interface controllers and keyboard controller bus, peripheral interface bus connected to the chip are mainly interrupt controllers, DMA controllers, timers / counters, parallel interfaces, keyboard interface and so on.
V. ISA bus
ISA industry standard bus is the IBM company in 1984 for the introduction of PC/AT machine to establish a 16-bit system bus standard, so also called AT bus ^ 14030301d ^ 4. ISA bus slot a **** there are 98 pins, the data rate of 8MB / s, but now the motherboard has been gradually canceled on the ISA bus support, such as 810, 815EP motherboards generally do not come with ISA slot (^14030301e^5 motherboard ISA interface enlargement).
VI, PCI bus
PCI bus is a kind of local bus not attached to a specific processor. From a structural point of view, PCI is inserted between the CPU and peripherals of the first level of bus, CPU bus and PCI bus by the bridge circuit connected to the PCI bus can be hooked up to graphics controllers, IDE devices, SCSI devices, network controllers, and other high-speed devices (^14030301f ^ 6 for the overall architecture of the PCI bus motherboard).
The PCI bus operates at a clock frequency of 33MHz, with a bit width of 32-bit (expandable to 64-bit) and a bandwidth of 133MB/s, allowing it to simultaneously support multiple peripheral devices and maintain high performance at high clock frequencies.The PCI bus supports bus master technology, which allows intelligent devices to take control of the bus when needed (^14030301g^7 is a zoomed-in view of the motherboard's PCI interface enlargement).
With the development of technology, the traditional 32-bit 33MHz PCI bus has been unable to meet the demand for all the devices in the system to transfer data, even after the improvement of the 64-bit 66MHz PCI-X bus (with a bandwidth of 533MB/s) used in servers and high-end computer systems is unable to meet the current demand, therefore, the motherboard chipset manufacturers are the motherboard's overall
1. Increase the system memory bus and front side bus bandwidth.
2. Transfer the original PCI bus to the Southbridge chip for management, and use it only for connecting devices on PCI expansion slots.
3. Increase the bandwidth of the bridge bus (former PCI bus) between the North and South Bridges.
4. Separate the display interface, which requires a large amount of data, from the original PCI bus in the form of an AGP bus, which is hooked up to the Northbridge chip and provides data for the display card alone.
VII. AGP Bus
AGP (Accelerated Graphics Port) is a bus specification designed to increase video bandwidth, first appearing in the 440LX chipset. In systems using AGP, the graphics card is connected to the main memory via the AGP bus, chipset, and directly reads the display data from the main memory, increasing the data transfer speed between the display chip and the main memory, reducing the load on the PCI bus, and facilitating the full performance of other PCI devices (^14030301g^7 Enlarged view of the motherboard's AGP interface).
The development of the AGP bus has gone through the stages of AGP1×, 2×, 4×, 8×, etc. The AGP bus operates at a clock frequency of 66MHz, with a bit width of 32 bits. 1× mode has a bandwidth of 266MB/s (66MHz x 32bit/8); 2× mode adopts a double-pulse-along data transfer technique, which allows for the transfer of data two times per clock cycle, increasing the bandwidth to 533MB/s (2×66MHz×32bit/8); 4× and 8× modes use a method of transmitting data 4 and 8 times per clock cycle (equivalent to increasing the AGP bus operating frequency), increasing the bandwidth to 1 GB/s (4×66MHz×32bit/8) and 2.1GB/s (8×66MHz×32bit/8) respectively.
AGP 8× is a newly released graphics port specification from Intel, supported by the world's major graphics chip suppliers and graphics card manufacturers such as ATi, NVIDIA, and Matrox. AGP 8× requires a large amount of data from the memory, and will be used primarily in Pentium 4 systems due to the fact that Pentium 4 motherboards support Rambus or DDR high-speed memory, the memory bus can provide 3.2GB/s of bandwidth, which is able to maximize the performance of AGP 8×.
Eight, South and North Bridge Bridge Buses
The PCI bus between the South and North Bridges on traditional 586-class motherboards provides data for the PCI cards in the PCI slots (display cards, sound cards, etc.) as well as the peripherals connected under the South Bridge chipset. Although the display interface, which requires a large amount of data in the later development, has been independent of the original PCI bus in the form of an AGP bus, only the 133MB/s data transfer rate is sufficient for a full HD 1080p video game. Although the display interface, which requires a large amount of data, is independent from the original PCI bus in the form of AGP bus in the later development, the traditional PCI bus with a data transmission bandwidth of 133MB/s is still unable to satisfy the needs of a large number of peripheral applications with increasing speed and increasing amount of data. Therefore, in recent years, motherboard chipset manufacturers have transferred the original PCI bus to the Southbridge chipset management, and transformed the bridge bus between the South and North Bridges with different programs.
Intel used a program called "Hub Link", which was first used in the i810 chipset (most of its subsequent i8xx chipsets also use this architecture). In the equivalent of the original north bridge chip and the original south bridge chip between the use of an 8 bit bit width, 133 MHz clock frequency and the use of double pulse along the data transfer technology bus, so that the data bandwidth to 266 MB / s (2 × 133MHz × 8bit / 8). In addition, the original PCI bus is hooked up to the ICH (Input/Output Controller Hub), thereby increasing the data transfer bandwidth between the North and South Bridges (^14030301h^8 for i845 chipset architecture).
VIA adopted a program called "V-Link", which first appeared in the VIA Apollo Pro266 chipset, V-Link technology will be the original PCI bus clock frequency from the original 33MHz to 66MHz, so that between the North and South Bridges of the bandwidth to increase to 266MB/s (66MHz x 32bit/8). At the same time, the original PCI bus was handed over to the Southbridge chip for management (^14030301i^9 for Apollo Pro266A chipset architecture).
SiS uses a solution called "Multi-Threaded I/O Link" (MuTIOL), which first appeared in its SiS 635 chipset, to prepare eight channels for peripherals that are 32 bits wide and clocked at 33.3 MHz. The MuTIOL technology prepares eight channels for peripherals with a bit width of 32 bits and a clock frequency of 33.3 MHz, for a total bandwidth of more than 1 GB/s.
The solution proposed by AMD, called the "Hyper Transport Bus", is supported by NVIDIA, Ali, and many other renowned vendors, and appeared for the first time in NVIDIA's nForce chipsets. The bandwidth of Hyper Transport bus has reached 12.8 GB/s, which is 96 times higher than that of the traditional PCI bus. Hyper Transport bus operates at a clock frequency of 400 MHz, and the maximum bandwidth is up to 800 MB/s due to the double-pulse along data transmission technology. The advantage of Hyper Transport bus is not only its speed, but also its "elastic data bandwidth" and other characteristics, which allows a 32-bit bus to transmit several groups of non-32-bit (4 Byte) data at the same time, thus speeding up the operation efficiency of the whole system.