DCSK program
Design of FM-DCSK communication system with dual DSP as the core
[Date: 2005-8-14] Source: Foreign Electronics Component author: Chen Li Wang Qiang [Font: Large, Medium, Small]
Abstract: Chaos secure communication using FM-DCSK modulation has better characteristics than other chaotic keying secure communications, but at the same time the circuit implementation is also more complex complex. DSP has broad application prospects in chaotic communications due to its high efficiency and flexibility. Based on the characteristics of TMS320C5402, this article provides a hardware solution for using two DSPs to implement an FM-DCSK communication system. At the same time, it also provides a hardware principle block diagram and software design process when the system works independently.
Keywords: digital signal processor (DSP); frequency modulation-differential chaos keying (FM-DCSK); chaotic communication; multi-channel buffered serial port
1 Introduction
In recent years, with the proposal and development of chaos synchronization and control theory, the application of chaos in the fields of signal processing, communication and control has become increasingly widespread. It is generally believed that in the field of communications, chaotic signals replace traditional sinusoidal signals as information carriers and have the following advantages: first, the broadband characteristics of chaotic signals can achieve a certain sense of spread spectrum; second, similar noise of chaotic signals is difficult to predict. This feature can provide guarantee for the confidential transmission of information.
Figure 1
There are many types of chaotic communication, among which the more promising ones are differential chaos keying (DCSK) and chaotic spread spectrum communication. Their most common feature is that the signal transmitted in the channel is no longer a coupled signal to achieve synchronization between the sending end and the receiving end, but uses the statistical characteristics of chaotic signals, that is, the autocorrelation and cross-correlation characteristics of chaotic signals to achieve a certain degree of synchronization. confidential communications. The current research work is mainly based on theoretical research and computer simulation, and there are few designs that use hardware to verify the communication performance of DCSK and its improved FM-DCSK. Therefore, the author designed a dual digital signal processor (DSP) based on FM-DCSK communication system scheme. The article introduces the voice terminal in the system, the generation of chaotic sequences and its FM modulation, DCSK modulation and demodulation and data communication circuits. It also analyzes the loading principle and feasibility of the program when the system is working. At the same time, the hardware principle block diagram and software design flow chart are given.
2 Overall system hardware structure
This system is mainly used to complete the collection of voice signals, voice compression coding and FM-DCSK modulation of voice signals, and pass the modulated data through The multi-channel buffered serial port (McBSP) of the DSP is sent out, and the received data is DCSK demodulated, voice decompressed and decoded at the same time, and the decoded data is D/A converted to restore the analog voice. This system uses the serial digital-to-analog/analog-to-digital conversion chip TLV320AIC10 to convert the input voice signal into a digital voice signal. After the processing is completed, the digital voice is converted into an analog voice signal; the low bit rate vocoder AMBE-1000 is used To perform low-rate speech compression encoding on digital speech signals and decode the DCSK demodulated data; TMS320C5402 (main) not only performs DC-SK modulation and DCSK demodulation on the encoded data, but also serves as the entire system The controller is used to complete the setting and control of each functional chip, and transfer data through the dual-port RAM chip (IDT7206) and TMS320C5402 (slave), and at the same time through the multi-channel buffered serial port (McBSP) and another TMS320C5402 (slave) Perform two-way data communication. TMS320C5402 (slave) completes the generation of chaotic sequence and the FM modulation operation of the sequence under the control of TMS320C5402 (master). The hardware principle of the entire system is shown in Figure 1.
In the figure, C5402 (master) uses parallel mode to load the program, while C5402 (slave) uses HPI mode to load the program. Since the program is not loaded in parallel through the dual-port RAM, the complex control process of the C5402 (master) when loading the program from the C5402 slave can be reduced and resources can be effectively utilized. When the system works independently, the communication between the C5402 master and slave is mainly completed through dual-port RAM.
3 System circuit working principle
This system includes voice terminal circuit, chaotic sequence generation and its FM modulation circuit, DCSK modulation and demodulation, and two system data communication implementation circuits. Each part completes two-way FM-DCSK communication under the coordination of the controller.
3.1 Voice terminal circuit
The voice terminal circuit is composed of the vocoder AMBE-1000 and the serial digital-to-analog/analog-to-digital conversion chip TLV320AIC10, which can be controlled by the DSP controller The digitization of analog voice is completed, and compression and encoding are performed to output framed coded data packets, which are then used as information data and then output after FM-DCSK modulation by DSP. At the same time, the received data packets demodulated by DSP are decoded to restore the digital voice, and finally the analog voice is output through D/A conversion.
In the hardware connection, the AMBE-1000's transmit and receive strobe signals and shift clock are all FS and CLKS signals generated by TLV320AIC10. In order to meet the timing requirements of AMBE-1000, TX_STRB and TX_O_CLK are directly connected to FS and CLKS generated by TLV320AIC10 respectively, while RX_STRB and RX_O_CLK are connected to FS and CLKS after CPLD logic conversion. The coding rate, channel interface mode, AD interface mode and various controls of AMBE-1000 are all completed by C5402 (master) by operating different I/O ports and latched by CPLD. The timing logic diagram of AMBE-1000 is as follows As shown in Figure 2.
The control of each control register in TLV320AIC10 can be completed by writing data in the corresponding format to DCSI through the multi-channel buffered serial port McBSP0 using C5402 (slave). The connection to the C5402 (slave) works in SPI mode, and the FS and CLKS signals are also generated by the TLV320AIC10. After the initialization is completed, the TLV320AIC10 exchanges data with the vocoder at a sampling rate of 8kHz and a linear quantization mode of 16bit. The vocoder exchanges data with the C5402 (master) every 20ms. Of course, all working methods can be realized through software programming.
3.2 The generation of chaotic sequence and its FM modulation
The generation of chaotic sequence and its FM modulation are mainly completed by C5402 (slave). Classic Logistic mapping can be used:
Then the required chaotic sequence is generated through discrete iterative operations. From the principle of FM-DCSK communication method, it can be known that the generated chaotic sequence needs to be FM modulated, and then the voice data can be DCSK modulated. The block diagram of the FM-DCSK modulation and demodulation system is shown in Figure 3. Because the amount of FM calculations in chaotic sequences is relatively large, TMS320C5402 is selected as the calculation processor in this design, and its maximum operating frequency can reach 100MHz.
C5402 (slave) sends the FM modulated chaos sequence to C5402 (master) through dual-port RAM, which is equivalent to completing the chaos generator and FM modulation in the FM-DCSK modulation and demodulation system. function of the device.
3.3 DCSK modulation, demodulation and data communication
C5402 can be used to complete the DCSK modulation of the low-rate encoded voice signal and the DCSK demodulation of the received data, and at the same time it can be controlled CPLD to generate various control signals. During each communication process, C5402 (master) will read the corresponding number of FM modulated chaotic sequences from the dual-port RAM, then perform DC-SK modulation on the received voice data bit by bit, and at the same time receive DCSK through McBSP in DMA mode. The data is modulated and DCSK demodulated by C5402 (master). Both tasks are completed through interrupts
3.4 Program loading process when the system works independently
The program loading of this system is divided into C5402 (main)'s own parallel There are two parts to loading and HPI loading of C5402(slave).
The logic between C5402 (main), Flash AT29LV1024 and dual-port RAM is shown in Figure 4.
When the C5402 (master) is loaded with power-on reset, since the Bootloader program sets XF to high level during initialization, after the system enters the parallel boot loader mode, the C5402 (master) will address the unit with data 0FFFFh (A15＝ 1. Select Flash) to read the first address of the program storage area to be loaded and the parallel loading data stream. At this time, C5402 can read the data in the Flash address 08000h-0FFFFh unit into the on-chip DRAM and off-chip SRAM of C5402 corresponding to the 0000h-7FFFh addressing area. After the boot-loader program ends, the first statement of the user program is RSBX XF, that is, setting the XF pin to low level, then the Flash will always be deactivated. In this way, the high 32k area (08000h-0FFFFh) of the dual-port RAM will be released and used as the data area or program area of ??the C5402? main runtime. The program data loaded in by C5402? Master is mainly divided into three parts: the loading program for C5402 (slave), its own running program and the running program of C5402 (slave).
During the parallel loading process of C5402 (master), C5402 (slave) will determine which loading mode it is. Because the HINT and INT2 of the C5402? slave are connected together, the 07FH unit will be cleared to 0 when the DSP is powered on and initialized. At the same time, setting HINT to 0 will cause the corresponding IFR flag bit of INT2 to be valid. The C5402 (slave) queries the flag of INT2 After the bit is valid, it is judged to be HPI loading mode. After C5402 (master) performs parallel loading, it will first run the loader to transfer the running program data of C5402 (slave) to C5402 (slave), thereby writing the program entry address of C5402 (slave) to unit 07FH, so This indicates that HPI loading is complete.
4 System software design
4.1 Program flow
The system software design mainly includes the programming of C5402 master and C5402 (slave). The software design of C5402?Master consists of C5402 initialization, AMBE-1000 initialization, McBSP0 and McB-SP1 initialization, DMA initialization, DSP interrupt setting, receiving data interrupt setting program and sending data interrupt setting program. Figure 5 is the C5402 (main) software system flow chart, Figure 6 and Figure 7 are the McBSP0 receive interrupt setting and McBSP1 receive interrupt setting flow charts respectively. The software design of C5402 (slave) consists of C5402 initialization, TLV320AIC10 initialization, chaotic sequence generation and FM modulation of the chaotic sequence.
4.2 Issues that should be paid attention to in program design
When designing system software, the following issues should be paid attention to:
(1) Due to the McBSP work In data reception interrupt mode, the corresponding bits of global interrupt and serial port interrupt must be set appropriately. At the same time, when setting the interrupt vector table, the location of the interrupt vector table should correspond to the interrupt vector pointer IPTR in the processor mode status register PMST. The 9-bit address of IPTR points to the program page where the 128-word interrupt vector is located. At the same time, the interrupt The vector table must also be written in strict accordance with the format specified by C5402, otherwise the required interrupt results cannot be generated correctly.
(2) To realize the offline and independent operation of the DSP data acquisition system, program loading is very critical. When C5402 (master) performs parallel loading, the program data flow in AT29LV1024 must strictly follow the parallel loading format to load the C5402 slave loader, C5402 (master) own execution program and C5402 (slave) program into the on-chip DRAM and Off-chip dual-port SRAM.
(3) When dual-port RAM transfers data between two DSPs, it is necessary to allocate space reasonably, coordinate the read and write timing, and strictly avoid data conflicts.
5 Conclusion
This article uses two TMS320C5402 to design the hardware implementation scheme of FM-DCSK communication system, and provides the hardware principle block diagram and software design flow chart when the system works independently.
Practice has proven that using parallel loading mode and HPI loading mode at the same time can effectively utilize system resources and reduce costs
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